Tegra194: mce: enable strict checking
"Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee <dilee@nvidia.com>
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@ -36,6 +36,12 @@
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******************************************************************************/
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#define MCE_STAT_ID_SHIFT 16U
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/*******************************************************************************
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* Security config macros
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******************************************************************************/
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#define STRICT_CHECKING_ENABLED_SET (1UL << 0)
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#define STRICT_CHECKING_LOCKED_SET (1UL << 1)
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/* declarations for NVG handler functions */
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uint64_t nvg_get_version(void);
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int32_t nvg_enable_power_perf_mode(void);
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@ -54,12 +60,16 @@ int32_t nvg_roc_clean_cache(void);
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int32_t nvg_roc_flush_cache(void);
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int32_t nvg_roc_clean_cache_trbits(void);
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int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
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void nvg_set_request_data(uint64_t req, uint64_t data);
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void nvg_set_request(uint64_t req);
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uint64_t nvg_get_result(void);
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uint64_t nvg_cache_clean(void);
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uint64_t nvg_cache_clean_inval(void);
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uint64_t nvg_cache_inval_all(void);
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int32_t nvg_roc_clean_cache_trbits(void);
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void nvg_enable_strict_checking_mode(void);
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/* MCE helper functions */
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void mce_enable_strict_checking(void);
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#endif /* __MCE_PRIVATE_H__ */
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@ -21,6 +21,7 @@
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#include <t194_nvg.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/* Handler to check if MCE firmware is supported */
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static bool mce_firmware_not_supported(void)
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@ -184,3 +185,53 @@ void mce_verify_firmware_version(void)
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panic();
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}
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}
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/*******************************************************************************
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* Handler to enable the strict checking mode
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******************************************************************************/
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void mce_enable_strict_checking(void)
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{
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uint64_t sctlr = read_sctlr_el3();
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int32_t ret = 0;
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if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
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/*
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* Step1: TZ-DRAM and TZRAM should be setup before the MMU is
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* enabled.
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*
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* The common code makes sure that TZDRAM/TZRAM are already
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* enabled before calling into this handler. If this is not the
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* case, the following sequence must be executed before moving
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* on to step 2.
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*
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* tlbialle1is();
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* tlbialle3is();
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* dsbsy();
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* isb();
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*
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*/
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if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) {
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tlbialle1is();
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tlbialle3is();
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dsbsy();
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isb();
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}
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/*
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* Step2: SCF flush - Clean and invalidate caches and clear the
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* TR-bits
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*/
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ret = nvg_roc_clean_cache_trbits();
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if (ret < 0) {
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ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
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ret);
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return;
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}
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/*
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* Step3: Issue the SECURITY_CONFIG request to MCE to enable
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* strict checking mode.
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*/
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nvg_enable_strict_checking_mode();
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}
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}
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@ -284,3 +284,16 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
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return ret;
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}
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/*
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* Enable strict checking mode
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*
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* NVGDATA[3] strict_check ON + lock
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*/
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void nvg_enable_strict_checking_mode(void)
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{
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uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
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STRICT_CHECKING_LOCKED_SET);
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nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
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}
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@ -17,6 +17,7 @@
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/psci/psci.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <plat/common/platform.h>
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#include <se.h>
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#include <smmu.h>
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@ -356,6 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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* context if we are.
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*/
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/*
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* Enable strict checking after programming the GSC for
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* enabling TZSRAM and TZDRAM
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*/
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mce_enable_strict_checking();
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/* Init SMMU */
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tegra_smmu_init();
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@ -19,6 +19,7 @@
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#include <drivers/arm/gicv2.h>
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#include <bl31/interrupt_mgmt.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <plat/common/platform.h>
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#include <tegra_def.h>
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#include <tegra_mc_def.h>
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@ -257,3 +258,12 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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}
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void plat_late_platform_setup(void)
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{
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/*
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* Enable strict checking after programming the GSC for
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* enabling TZSRAM and TZDRAM
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*/
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mce_enable_strict_checking();
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}
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