drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Grzegorz Jaszczyk
Manish Pandey
parent
dceac436f6
commit
ad416958d9
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@ -0,0 +1,253 @@
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include <mvebu.h>
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#include <stdbool.h>
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#include "dfx.h"
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/* #define DEBUG_DFX */
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#ifdef DEBUG_DFX
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#define debug(format...) NOTICE(format)
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#else
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#define debug(format, arg...)
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#endif
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#define TSEN_CTRL0 0xf06f8084
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#define TSEN_CTRL0_START BIT(0)
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#define TSEN_CTRL0_RESET BIT(1)
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#define TSEN_CTRL0_ENABLE BIT(2)
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#define TSEN_CTRL0_AVG_BYPASS BIT(6)
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#define TSEN_CTRL0_CHAN_SHIFT 13
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#define TSEN_CTRL0_CHAN_MASK 0xF
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#define TSEN_CTRL0_OSR_SHIFT 24
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#define TSEN_CTRL0_OSR_MAX 0x3
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#define TSEN_CTRL0_MODE_SHIFT 30
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#define TSEN_CTRL0_MODE_EXTERNAL 0x2U
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#define TSEN_CTRL0_MODE_MASK 0x3U
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#define TSEN_CTRL1 0xf06f8088
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#define TSEN_CTRL1_INT_EN BIT(25)
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#define TSEN_CTRL1_HYST_SHIFT 19
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#define TSEN_CTRL1_HYST_MASK (0x3 << TSEN_CTRL1_HYST_SHIFT)
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#define TSEN_CTRL1_THRESH_SHIFT 3
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#define TSEN_CTRL1_THRESH_MASK (0x3ff << TSEN_CTRL1_THRESH_SHIFT)
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#define TSEN_STATUS 0xf06f808c
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#define TSEN_STATUS_VALID_OFFSET 16
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#define TSEN_STATUS_VALID_MASK (0x1 << TSEN_STATUS_VALID_OFFSET)
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#define TSEN_STATUS_TEMP_OUT_OFFSET 0
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#define TSEN_STATUS_TEMP_OUT_MASK (0x3FF << TSEN_STATUS_TEMP_OUT_OFFSET)
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#define DFX_SERVER_IRQ_SUM_MASK_REG 0xf06f8104
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#define DFX_SERVER_IRQ_EN BIT(1)
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#define DFX_IRQ_CAUSE_REG 0xf06f8108
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#define DFX_IRQ_MASK_REG 0xf06f810c
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#define DFX_IRQ_TSEN_OVERHEAT_OFFSET BIT(22)
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#define THERMAL_SEN_OUTPUT_MSB 512
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#define THERMAL_SEN_OUTPUT_COMP 1024
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#define COEF_M 423
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#define COEF_B -150000LL
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static void armada_ap806_thermal_read(u_register_t *temp)
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{
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uint32_t reg;
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reg = mmio_read_32(TSEN_STATUS);
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reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >>
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TSEN_STATUS_TEMP_OUT_OFFSET);
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/*
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* TSEN output format is signed as a 2s complement number
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* ranging from-512 to +511. when MSB is set, need to
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* calculate the complement number
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*/
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if (reg >= THERMAL_SEN_OUTPUT_MSB)
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reg -= THERMAL_SEN_OUTPUT_COMP;
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*temp = ((COEF_M * ((signed int)reg)) - COEF_B);
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}
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static void armada_ap806_thermal_irq(void)
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{
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/* Dummy read, register ROC */
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mmio_read_32(DFX_IRQ_CAUSE_REG);
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}
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static void armada_ap806_thermal_overheat_irq_init(void)
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{
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uint32_t reg;
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/* Clear DFX temperature IRQ cause */
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reg = mmio_read_32(DFX_IRQ_CAUSE_REG);
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/* Enable DFX Temperature IRQ */
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reg = mmio_read_32(DFX_IRQ_MASK_REG);
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reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET;
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mmio_write_32(DFX_IRQ_MASK_REG, reg);
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/* Enable DFX server IRQ */
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reg = mmio_read_32(DFX_SERVER_IRQ_SUM_MASK_REG);
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reg |= DFX_SERVER_IRQ_EN;
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mmio_write_32(DFX_SERVER_IRQ_SUM_MASK_REG, reg);
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/* Enable overheat interrupt */
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reg = mmio_read_32(TSEN_CTRL1);
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reg |= TSEN_CTRL1_INT_EN;
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mmio_write_32(TSEN_CTRL1, reg);
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}
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static unsigned int armada_mc_to_reg_temp(unsigned int temp_mc)
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{
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unsigned int sample;
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sample = (temp_mc + COEF_B) / COEF_M;
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return sample & 0x3ff;
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}
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/*
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* The documentation states:
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* high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
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* which is the mathematical derivation for:
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* 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
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*/
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static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
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static unsigned int armada_mc_to_reg_hyst(int hyst_mc)
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{
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int i;
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/*
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* We will always take the smallest possible hysteresis to avoid risking
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* the hardware integrity by enlarging the threshold by +8°C in the
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* worst case.
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*/
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for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
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if (hyst_mc >= hyst_levels_mc[i])
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break;
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return i;
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}
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static void armada_ap806_thermal_threshold(int thresh_mc, int hyst_mc)
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{
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uint32_t ctrl1;
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unsigned int threshold = armada_mc_to_reg_temp(thresh_mc);
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unsigned int hysteresis = armada_mc_to_reg_hyst(hyst_mc);
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ctrl1 = mmio_read_32(TSEN_CTRL1);
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/* Set Threshold */
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if (thresh_mc >= 0) {
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ctrl1 &= ~(TSEN_CTRL1_THRESH_MASK);
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ctrl1 |= threshold << TSEN_CTRL1_THRESH_SHIFT;
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}
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/* Set Hysteresis */
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if (hyst_mc >= 0) {
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ctrl1 &= ~(TSEN_CTRL1_HYST_MASK);
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ctrl1 |= hysteresis << TSEN_CTRL1_HYST_SHIFT;
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}
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mmio_write_32(TSEN_CTRL1, ctrl1);
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}
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static void armada_select_channel(int channel)
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{
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uint32_t ctrl0;
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/* Stop the measurements */
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ctrl0 = mmio_read_32(TSEN_CTRL0);
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ctrl0 &= ~TSEN_CTRL0_START;
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mmio_write_32(TSEN_CTRL0, ctrl0);
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/* Reset the mode, internal sensor will be automatically selected */
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ctrl0 &= ~(TSEN_CTRL0_MODE_MASK << TSEN_CTRL0_MODE_SHIFT);
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/* Other channels are external and should be selected accordingly */
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if (channel) {
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/* Change the mode to external */
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ctrl0 |= TSEN_CTRL0_MODE_EXTERNAL <<
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TSEN_CTRL0_MODE_SHIFT;
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/* Select the sensor */
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ctrl0 &= ~(TSEN_CTRL0_CHAN_MASK << TSEN_CTRL0_CHAN_SHIFT);
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ctrl0 |= (channel - 1) << TSEN_CTRL0_CHAN_SHIFT;
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}
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/* Actually set the mode/channel */
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mmio_write_32(TSEN_CTRL0, ctrl0);
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/* Re-start the measurements */
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ctrl0 |= TSEN_CTRL0_START;
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mmio_write_32(TSEN_CTRL0, ctrl0);
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}
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static void armada_ap806_thermal_init(void)
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{
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uint32_t reg;
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reg = mmio_read_32(TSEN_CTRL0);
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reg &= ~TSEN_CTRL0_RESET;
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reg |= TSEN_CTRL0_START | TSEN_CTRL0_ENABLE;
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/* Sample every ~2ms */
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reg |= TSEN_CTRL0_OSR_MAX << TSEN_CTRL0_OSR_SHIFT;
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/* Enable average (2 samples by default) */
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reg &= ~TSEN_CTRL0_AVG_BYPASS;
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mmio_write_32(TSEN_CTRL0, reg);
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debug("thermal: Initialization done\n");
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}
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static void armada_is_valid(u_register_t *read)
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{
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*read = (mmio_read_32(TSEN_STATUS) & TSEN_STATUS_VALID_MASK);
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}
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int mvebu_dfx_handle(u_register_t func, u_register_t *read, u_register_t x2,
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u_register_t x3)
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{
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debug_enter();
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switch (func) {
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case MV_SIP_DFX_THERMAL_INIT:
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armada_ap806_thermal_init();
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break;
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case MV_SIP_DFX_THERMAL_READ:
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armada_ap806_thermal_read(read);
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break;
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case MV_SIP_DFX_THERMAL_IRQ:
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armada_ap806_thermal_irq();
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break;
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case MV_SIP_DFX_THERMAL_THRESH:
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armada_ap806_thermal_threshold(x2, x3);
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armada_ap806_thermal_overheat_irq_init();
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break;
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case MV_SIP_DFX_THERMAL_IS_VALID:
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armada_is_valid(read);
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break;
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case MV_SIP_DFX_THERMAL_SEL_CHANNEL:
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armada_select_channel(x2);
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break;
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default:
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ERROR("unsupported dfx func\n");
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return -EINVAL;
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}
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debug_exit();
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return 0;
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}
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@ -0,0 +1,17 @@
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* DFX sub-FID */
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#define MV_SIP_DFX_THERMAL_INIT 1
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#define MV_SIP_DFX_THERMAL_READ 2
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#define MV_SIP_DFX_THERMAL_IS_VALID 3
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#define MV_SIP_DFX_THERMAL_IRQ 4
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#define MV_SIP_DFX_THERMAL_THRESH 5
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#define MV_SIP_DFX_THERMAL_SEL_CHANNEL 6
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int mvebu_dfx_handle(u_register_t func, u_register_t *read, u_register_t x2,
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u_register_t x3);
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@ -112,9 +112,10 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \
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$(MARVELL_DRV_BASE)/amb_adec.c \
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$(MARVELL_DRV_BASE)/ccu.c \
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$(MARVELL_DRV_BASE)/cache_llc.c \
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$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
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$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
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$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
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$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
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$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
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$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
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$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
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drivers/rambus/trng_ip_76.c
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BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c
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@ -16,6 +16,7 @@
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#include <plat_marvell.h>
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#include "comphy/phy-comphy-cp110.h"
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#include "secure_dfx_access/dfx.h"
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#include <stdbool.h>
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/* #define DEBUG_COMPHY */
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@ -37,6 +38,7 @@
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#define MV_SIP_LLC_ENABLE 0x82000011
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#define MV_SIP_PMU_IRQ_ENABLE 0x82000012
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#define MV_SIP_PMU_IRQ_DISABLE 0x82000013
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#define MV_SIP_DFX 0x82000014
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/* TRNG */
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#define MV_SIP_RNG_64 0xC200FF11
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@ -71,7 +73,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
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void *handle,
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u_register_t flags)
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{
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u_register_t ret;
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u_register_t ret, read;
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uint32_t w2[2] = {0, 0};
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int i;
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@ -136,6 +138,9 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
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mvebu_pmu_interrupt_disable();
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SMC_RET1(handle, 0);
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#endif
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case MV_SIP_DFX:
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ret = mvebu_dfx_handle(x1, &read, x2, x3);
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SMC_RET2(handle, ret, read);
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case MV_SIP_RNG_64:
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ret = eip76_rng_get_random((uint8_t *)&w2, 4 * (x1 % 2 + 1));
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SMC_RET3(handle, ret, w2[0], w2[1]);
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