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Tegra: enable EHF for watchdog timer interrupts 

This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.

Verified that the watchdog timer interrupt fires after migrating to
the EHF.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
This commit is contained in:
Varun Wadekar 2020-03-31 18:42:59 -07:00
parent 25d819a308
commit adb20a1755
6 changed files with 30 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
plat/nvidia/tegra/common/tegra_fiq_glue.c
View File

@ -9,6 +9,7 @@
#include <arch_helpers.h>
#include <bl31/interrupt_mgmt.h>
#include <bl31/ehf.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
@ -25,6 +26,15 @@
/* Legacy FIQ used by earlier Tegra platforms */
#define LEGACY_FIQ_PPI_WDT 28U
/* Install priority level descriptors for each dispatcher */
ehf_pri_desc_t plat_exceptions[] = {
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_TEGRA_WDT_PRIO),
};
/* Expose priority descriptors to Exception Handling Framework */
EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions),
PLAT_PRI_BITS);
/*******************************************************************************
* Static variables
******************************************************************************/
@ -35,26 +45,17 @@ static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
/*******************************************************************************
* Handler for FIQ interrupts
******************************************************************************/
static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
uint32_t flags,
void *handle,
void *cookie)
static int tegra_fiq_interrupt_handler(unsigned int id, unsigned int flags,
void *handle, void *cookie)
{
cpu_context_t *ctx = cm_get_context(NON_SECURE);
el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
uint32_t cpu = plat_my_core_pos();
uint32_t irq;
(void)id;
(void)flags;
(void)handle;
(void)cookie;
/*
* Read the pending interrupt ID
*/
irq = plat_ic_get_pending_interrupt_id();
/*
* Jump to NS world only if the NS world's FIQ handler has
* been registered
@ -90,7 +91,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
* disable the routing so that we can mark it as "complete" in the
* GIC later.
*/
if (irq == LEGACY_FIQ_PPI_WDT) {
if (id == LEGACY_FIQ_PPI_WDT) {
tegra_fc_disable_fiq_to_ccplex_routing();
}
#endif
@ -98,10 +99,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
/*
* Mark this interrupt as complete to avoid a FIQ storm.
*/
if (irq < 1022U) {
(void)plat_ic_acknowledge_interrupt();
plat_ic_end_of_interrupt(irq);
}
plat_ic_end_of_interrupt(id);
return 0;
}
@ -111,23 +109,13 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
******************************************************************************/
void tegra_fiq_handler_setup(void)
{
uint32_t flags;
int32_t rc;
/* return if already registered */
if (fiq_handler_active == 0U) {
/*
* Register an interrupt handler for FIQ interrupts generated for
* NS interrupt sources
*/
flags = 0U;
set_interrupt_rm_flag((flags), (NON_SECURE));
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
tegra_fiq_interrupt_handler,
flags);
if (rc != 0) {
panic();
}
ehf_register_priority_handler(PLAT_TEGRA_WDT_PRIO, tegra_fiq_interrupt_handler);
/* handler is now active */
fiq_handler_active = 1;

5
plat/nvidia/tegra/include/platform_def.h
View File

@ -86,5 +86,10 @@
#define MAX_IO_DEVICES U(0)
#define MAX_IO_HANDLES U(0)
/*******************************************************************************
* Platform macros to support exception handling framework
******************************************************************************/
#define PLAT_PRI_BITS U(3)
#define PLAT_TEGRA_WDT_PRIO U(0x40)
#endif /* PLATFORM_DEF_H */

4
plat/nvidia/tegra/platform.mk
View File

@ -20,6 +20,10 @@ $(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
PLAT_XLAT_TABLES_DYNAMIC := 1
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
# Enable exception handling at EL3
EL3_EXCEPTION_HANDLING := 1
GICV2_G0_FOR_EL3 := 1
# Enable PSCI v1.0 extended state ID format
PSCI_EXTENDED_STATE_ID := 1

4
plat/nvidia/tegra/soc/t186/plat_setup.c
View File

@ -214,9 +214,9 @@ void plat_late_platform_setup(void)
/* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra186_interrupt_props[] = {
INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};

4
plat/nvidia/tegra/soc/t194/plat_setup.c
View File

@ -275,9 +275,9 @@ void plat_early_platform_setup(void)
/* Secure IRQs for Tegra194 */
static const interrupt_prop_t tegra194_interrupt_props[] = {
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};

4
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -179,9 +179,9 @@ void plat_early_platform_setup(void)
/* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra210_interrupt_props[] = {
INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
};