Tegra: enable EHF for watchdog timer interrupts
This patch enables the Exception Handling Framework to service the WDT interrupts on all Tegra platforms. Verified that the watchdog timer interrupt fires after migrating to the EHF. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
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@ -9,6 +9,7 @@
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <bl31/interrupt_mgmt.h>
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#include <bl31/interrupt_mgmt.h>
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#include <bl31/ehf.h>
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#include <common/bl_common.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <context.h>
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#include <context.h>
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@ -25,6 +26,15 @@
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/* Legacy FIQ used by earlier Tegra platforms */
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/* Legacy FIQ used by earlier Tegra platforms */
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#define LEGACY_FIQ_PPI_WDT 28U
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#define LEGACY_FIQ_PPI_WDT 28U
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/* Install priority level descriptors for each dispatcher */
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ehf_pri_desc_t plat_exceptions[] = {
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EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_TEGRA_WDT_PRIO),
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};
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/* Expose priority descriptors to Exception Handling Framework */
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EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions),
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PLAT_PRI_BITS);
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/*******************************************************************************
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/*******************************************************************************
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* Static variables
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* Static variables
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******************************************************************************/
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******************************************************************************/
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@ -35,26 +45,17 @@ static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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/*******************************************************************************
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* Handler for FIQ interrupts
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* Handler for FIQ interrupts
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******************************************************************************/
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******************************************************************************/
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static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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static int tegra_fiq_interrupt_handler(unsigned int id, unsigned int flags,
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uint32_t flags,
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void *handle, void *cookie)
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void *handle,
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void *cookie)
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{
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
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el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
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uint32_t cpu = plat_my_core_pos();
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uint32_t cpu = plat_my_core_pos();
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uint32_t irq;
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(void)id;
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(void)flags;
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(void)flags;
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(void)handle;
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(void)handle;
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(void)cookie;
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(void)cookie;
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/*
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* Read the pending interrupt ID
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*/
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irq = plat_ic_get_pending_interrupt_id();
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/*
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/*
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* Jump to NS world only if the NS world's FIQ handler has
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* Jump to NS world only if the NS world's FIQ handler has
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* been registered
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* been registered
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@ -90,7 +91,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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* disable the routing so that we can mark it as "complete" in the
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* disable the routing so that we can mark it as "complete" in the
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* GIC later.
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* GIC later.
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*/
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*/
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if (irq == LEGACY_FIQ_PPI_WDT) {
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if (id == LEGACY_FIQ_PPI_WDT) {
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tegra_fc_disable_fiq_to_ccplex_routing();
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tegra_fc_disable_fiq_to_ccplex_routing();
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}
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}
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#endif
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#endif
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@ -98,10 +99,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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/*
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/*
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* Mark this interrupt as complete to avoid a FIQ storm.
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* Mark this interrupt as complete to avoid a FIQ storm.
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*/
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*/
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if (irq < 1022U) {
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plat_ic_end_of_interrupt(id);
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(void)plat_ic_acknowledge_interrupt();
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plat_ic_end_of_interrupt(irq);
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}
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return 0;
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return 0;
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}
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}
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@ -111,23 +109,13 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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******************************************************************************/
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******************************************************************************/
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void tegra_fiq_handler_setup(void)
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void tegra_fiq_handler_setup(void)
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{
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{
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uint32_t flags;
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int32_t rc;
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/* return if already registered */
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/* return if already registered */
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if (fiq_handler_active == 0U) {
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if (fiq_handler_active == 0U) {
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/*
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/*
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* Register an interrupt handler for FIQ interrupts generated for
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* Register an interrupt handler for FIQ interrupts generated for
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* NS interrupt sources
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* NS interrupt sources
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*/
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*/
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flags = 0U;
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ehf_register_priority_handler(PLAT_TEGRA_WDT_PRIO, tegra_fiq_interrupt_handler);
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set_interrupt_rm_flag((flags), (NON_SECURE));
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rc = register_interrupt_type_handler(INTR_TYPE_EL3,
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tegra_fiq_interrupt_handler,
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flags);
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if (rc != 0) {
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panic();
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}
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/* handler is now active */
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/* handler is now active */
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fiq_handler_active = 1;
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fiq_handler_active = 1;
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@ -86,5 +86,10 @@
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#define MAX_IO_DEVICES U(0)
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#define MAX_IO_DEVICES U(0)
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#define MAX_IO_HANDLES U(0)
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#define MAX_IO_HANDLES U(0)
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/*******************************************************************************
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* Platform macros to support exception handling framework
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******************************************************************************/
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#define PLAT_PRI_BITS U(3)
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#define PLAT_TEGRA_WDT_PRIO U(0x40)
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#endif /* PLATFORM_DEF_H */
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#endif /* PLATFORM_DEF_H */
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@ -20,6 +20,10 @@ $(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
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PLAT_XLAT_TABLES_DYNAMIC := 1
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PLAT_XLAT_TABLES_DYNAMIC := 1
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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# Enable exception handling at EL3
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EL3_EXCEPTION_HANDLING := 1
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GICV2_G0_FOR_EL3 := 1
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# Enable PSCI v1.0 extended state ID format
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# Enable PSCI v1.0 extended state ID format
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PSCI_EXTENDED_STATE_ID := 1
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PSCI_EXTENDED_STATE_ID := 1
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@ -214,9 +214,9 @@ void plat_late_platform_setup(void)
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/* Secure IRQs for Tegra186 */
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/* Secure IRQs for Tegra186 */
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static const interrupt_prop_t tegra186_interrupt_props[] = {
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static const interrupt_prop_t tegra186_interrupt_props[] = {
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INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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};
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};
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@ -275,9 +275,9 @@ void plat_early_platform_setup(void)
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/* Secure IRQs for Tegra194 */
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/* Secure IRQs for Tegra194 */
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static const interrupt_prop_t tegra194_interrupt_props[] = {
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static const interrupt_prop_t tegra194_interrupt_props[] = {
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INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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};
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};
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@ -179,9 +179,9 @@ void plat_early_platform_setup(void)
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/* Secure IRQs for Tegra186 */
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/* Secure IRQs for Tegra186 */
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static const interrupt_prop_t tegra210_interrupt_props[] = {
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static const interrupt_prop_t tegra210_interrupt_props[] = {
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INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
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INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, PLAT_TEGRA_WDT_PRIO,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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};
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};
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