Tegra: allow platforms to override plat_core_pos_by_mpidr()
This patch makes the default implementation of plat_core_pos_by_mpidr() as weakly linked, so that platforms can override it with their own. Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own implementation of plat_core_pos_by_mpidr(). Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -33,6 +33,7 @@
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#include <psci.h>
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#include <psci.h>
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extern const unsigned char tegra_power_domain_tree_desc[];
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extern const unsigned char tegra_power_domain_tree_desc[];
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#pragma weak plat_core_pos_by_mpidr
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/*******************************************************************************
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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* This function returns the Tegra default topology tree information.
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@ -52,23 +53,18 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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{
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unsigned int cluster_id, cpu_id;
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unsigned int cluster_id, cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
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return -1;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return -1;
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return PSCI_E_NOT_PRESENT;
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/*
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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* one of the two clusters present on the platform.
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*/
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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return -1;
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return PSCI_E_NOT_PRESENT;
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return (cpu_id + (cluster_id * 4));
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return (cpu_id + (cluster_id * 4));
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}
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}
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@ -49,6 +49,13 @@
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
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extern uint64_t tegra_enable_l2_ecc_parity_prot;
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extern uint64_t tegra_enable_l2_ecc_parity_prot;
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/*******************************************************************************
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* Tegra186 CPU numbers in cluster #0
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*******************************************************************************
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*/
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#define TEGRA186_CLUSTER0_CORE2 2
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#define TEGRA186_CLUSTER0_CORE3 3
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/*******************************************************************************
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* single root node. The first entry in the power domain descriptor specifies
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@ -256,3 +263,40 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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}
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id, pos;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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/*
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* Validate cluster_id by checking whether it represents
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* one of the two clusters present on the platform.
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*/
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return PSCI_E_NOT_PRESENT;
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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return PSCI_E_NOT_PRESENT;
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/* calculate the core position */
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pos = cpu_id + (cluster_id << 2);
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/* check for non-existent CPUs */
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if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
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return PSCI_E_NOT_PRESENT;
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return pos;
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}
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