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Tegra: sip_calls: fix defects flagged by MISRA scan 

Main fixes:

* Expressions resulting from the expansion of macro parameters
  shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
  to be compatible with whatever operation they're used in [Rule
  10.1]
* Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Anthony Zhou 2017-03-01 12:47:37 +08:00 committed by Varun Wadekar
parent 592035d05b
commit aeafc36212
1 changed files with 91 additions and 89 deletions
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30
plat/nvidia/tegra/common/tegra_sip_calls.c
View File

@ -31,12 +31,11 @@
******************************************************************************/
extern uint8_t tegra_fake_system_suspend;
/*******************************************************************************
* SoC specific SiP handler
******************************************************************************/
#pragma weak plat_sip_handler
int plat_sip_handler(uint32_t smc_fid,
int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@ -75,9 +74,12 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
/* Check if this is a SoC specific SiP */
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
if (err == 0)
if (err == 0) {
SMC_RET1(handle, (uint64_t)err);
} else {
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
@ -90,13 +92,14 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
if (err)
SMC_RET1(handle, err);
if (err != 0) {
SMC_RET1(handle, (uint64_t)err);
}
/*
* Check if Video Memory is aligned to 1MB.
*/
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
if (((x1 & 0xFFFFFU) != 0U) || ((x2 & 0xFFFFFU) != 0U)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
@ -108,16 +111,15 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
*/
regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
TEGRA_GPU_RESET_REG_OFFSET);
if ((regval & GPU_RESET_BIT) == 0U) {
if ((regval & GPU_RESET_BIT) == 0UL) {
ERROR("GPU not in reset! Video Memory setup failed\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
tegra_memctrl_videomem_setup(x1, (uint32_t)x2);
SMC_RET1(handle, 0);
break;
/*
* The NS world registers the address of its handler to be
@ -127,8 +129,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
*/
case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
if (!x1)
if (x1 == 0U) {
SMC_RET1(handle, SMC_UNK);
}
/*
* TODO: Check if x1 contains a valid DRAM address
@ -138,7 +141,6 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
tegra_fiq_set_ns_entrypoint(x1);
SMC_RET1(handle, 0);
break;
/*
* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
@ -149,10 +151,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
/* retrieve context registers when FIQ triggered */
tegra_fiq_get_intr_context();
(void)tegra_fiq_get_intr_context();
SMC_RET0(handle);
break;
case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
/*
@ -162,7 +163,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
* platform needs. These include replacing the call to WFI by
* a warm reset request.
*/
if (tegra_platform_is_emulation() != 0U) {
if (tegra_platform_is_virt_dev_kit() != false) {
tegra_fake_system_suspend = 1;
SMC_RET1(handle, 0);
@ -178,6 +179,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}
}
SMC_RET1(handle, SMC_UNK);
}