Release v1.4: update change-log.rst
Updated change-log.rst with summary of changes since release v1.3. Change-Id: Iecd31ed315bd9ad7ffe8bce6550f7c90e1e3a9b0 Signed-off-by: David Cunado <david.cunado@arm.com>
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David Cunado
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.. contents::
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ARM Trusted Firmware - version 1.4
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==================================
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New features
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------------
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- Enabled support for platforms with hardware assisted coherency.
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A new build option HW_ASSISTED_COHERENCY allows platforms to take advantage
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of the following optimisations:
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- Skip performing cache maintenance during power-up and power-down.
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- Use spin-locks instead of bakery locks.
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- Enable data caches early on warm-booted CPUs.
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- Added support for Cortex-A75 and Cortex-A55 processors.
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Both Cortex-A75 and Cortex-A55 processors use the ARM DynamIQ Shared Unit
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(DSU). The power-down and power-up sequences are therefore mostly managed in
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hardware, reducing complexity of the software operations.
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- Introduced ARM GIC-600 driver.
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ARM GIC-600 IP complies with ARM GICv3 architecture. For FVP platforms, the
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GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600.
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- Updated GICv3 support:
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- Introduced power management APIs for GICv3 Redistributor. These APIs
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allow platforms to power down the Redistributor during CPU power on/off.
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Requires the GICv3 implementations to have power management operations.
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Implemented the power management APIs for FVP.
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- GIC driver data is flushed by the primary CPU so that secondary CPU do
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not read stale GIC data.
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- Added support for ARM System Control and Management Interface v1.0 (SCMI).
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The SCMI driver implements the power domain management and system power
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management protocol of the SCMI specification (ARM DEN 0056ASCMI) for
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communicating with any compliant power controller.
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Support is added for the Juno platform. The driver can be found in the
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plat/arm/css/drivers folder.
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- Added support to enable pre-integration of TBB with the ARM TrustZone
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CryptoCell product, to take advantage of its hardware Root of Trust and
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crypto acceleration services.
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- Enabled Statistical Profiling Extensions for lower ELs.
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The firmware support is limited to the use of SPE in the Non-secure state
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and accesses to the SPE specific registers from S-EL1 will trap to EL3.
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The SPE are architecturally specified for AArch64 only.
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- Code hygiene changes aligned with MISRA guidelines:
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- Fixed signed / unsigned comparison warnings in the translation table
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library.
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- Added U(_x) macro and together with the existing ULL(_x) macro fixed
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some of the signed-ness defects flagged by the MISRA scanner.
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- Enhancements to Firmware Update feature:
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- The FWU logic now checks for overlapping images to prevent execution of
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unauthenticated arbitary code.
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- Introduced new FWU_SMC_IMAGE_RESET SMC that changes the image loading
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state machine to go from COPYING, COPIED or AUTHENTICATED states to
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RESET state. Previously, this was only possible when the authentication
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of an image failed or when the execution of the image finished.
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- Fixed integer overflow which addressed TFV-1: Malformed Firmware Update
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SMC can result in copy of unexpectedly large data into secure memory.
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- Introduced support for ARM Compiler 6 and LLVM (clang).
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ARM TF can now also be built with the ARM Compiler 6 or the clang compilers.
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The assembler and linker must be provided by the GNU toolchain.
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Tested with ARM CC 6.7 and clang 3.9.x and 4.0.x.
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- Memory footprint improvements:
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- Introduced `tf_snprintf`, a reduced version of `snprintf` which has
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support for a limited set of formats.
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The mbedtls driver is updated to optionally use `tf_snprintf` instead of
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`snprintf`.
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- The `assert()` is updated to no longer print the function name, and
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additional logging options are supported via an optional platform define
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`PLAT_LOG_LEVEL_ASSERT`, which controls how verbose the assert output is.
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- Enhancements to Trusted Firmware support when running in AArch32 execution
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state:
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- Support booting SP_MIN and BL33 in AArch32 execution mode on Juno. Due to
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hardware limitations, BL1 and BL2 boot in AArch64 state and there is
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additional trampoline code to warm reset into SP_MIN in AArch32 execution
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state.
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- Added support for ARM Cortex-A53/57/72 MPCore processors including the
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errata workarounds that are already implemented for AArch64 execution
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state.
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- For FVP platforms, added AArch32 Trusted Board Boot support, including the
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Firmware Update feature.
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- Introduced ARM SiP service for use by ARM standard platforms.
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- Added new ARM SiP Service SMCs to enable the Non-secure world to read PMF
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timestamps.
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Added PMF instrumentation points in ARM TF in order to quantify the
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overall time spent in the PSCI software implementation.
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- Added new ARM SiP service SMC to switch execution state.
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This allows the lower exception level to change its execution state from
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AArch64 to AArch32, or vice verse, via a request to EL3.
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- Migrated to use SPDX[0] license identifiers to make software license
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auditing simpler.
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*NOTE:* Files that have been imported by FreeBSD have not been modified.
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[0]: https://spdx.org/
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- Enhancements to the translation table library:
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- Added version 2 of translation table library that allows different
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translation tables to be modified by using different 'contexts'. Version 1
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of the transalation table library only allows the current EL's translation
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tables to be modified.
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Version 2 of the translation table also added support for dynamic
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regions; regions that can be added and removed dynamically whilst the
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MMU is enabled. Static regions can only be added or removed before the
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MMU is enabled.
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The dynamic mapping functionality is enabled or disabled when compiling
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by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can
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be done per-image.
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- Added support for translation regimes with two virtual address spaces
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such as the one shared by EL1 and EL0.
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The library does not support initializing translation tables for EL0
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software.
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- Added support to mark the translation tables as non-cacheable using an
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additional build option `XLAT_TABLE_NC`.
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- Added support for GCC stack protection. A new build option
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ENABLE_STACK_PROTECTOR was introduced that enables compilation of all BL
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images with one of the GCC -fstack-protector-* options.
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A new platform function plat_get_stack_protector_canary() was introduced
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that returns a value used to initialize the canary for stack corruption
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detection. For increased effectiveness of protection platforms must provide
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an implementation that returns a random value.
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- Enhanced support for ARM platforms:
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- Added support for multi-threading CPUs, indicated by `MT` field in MPDIR.
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A new build flag `ARM_PLAT_MT` is added, and when enabled, the functions
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accessing MPIDR assume that the `MT` bit is set for the platform and
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access the bit fields accordingly.
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Also, a new API `plat_arm_get_cpu_pe_count` is added when `ARM_PLAT_MT` is
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enabled, returning the Processing Element count within the physical CPU
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corresponding to `mpidr`.
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- The ARM platforms migrated to use version 2 of the translation tables.
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- Introduced a new ARM platform layer API `plat_arm_psci_override_pm_ops`
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which allows ARM platforms to modify `plat_arm_psci_pm_ops` and therefore
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dynamically define PSCI capability.
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- The ARM platforms migrated to use IMAGE_LOAD_V2 by default.
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- Enhanced reporting of errata workaround status with the following policy:
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- If an errata workaround is enabled:
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- If it applies (i.e. the CPU is affected by the errata), an INFO message
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is printed, confirming that the errata workaround has been applied.
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- If it does not apply, a VERBOSE message is printed, confirming that the
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errata workaround has been skipped.
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- If an errata workaround is not enabled, but would have applied had it
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been, a WARN message is printed, alerting that errata workaround is
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missing.
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- Added build options ARM_ARCH_MAJOR and ARM_ARM_MINOR to choose the
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architecture version to target ARM TF.
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- Updated the spin lock implementation to use the more efficient CAS (Compare
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And Swap) instruction when available. This instruction was introduced in
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ARMv8.1-A.
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- Applied errata workaround for ARM Cortex-A53: 855873.
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- Applied errata workaround for ARM-Cortex-A57: 813419.
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- Enabled all A53 and A57 errata workarounds for Juno, both in AArch64 and
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AArch32 execution states.
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- Added support for Socionext UniPhier SoC platform.
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- Added support for Hikey960 and Hikey platforms.
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- Added support for Rockchip RK3328 platform.
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- Added support for NVidia Tegra T186 platform.
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- Added support for Designware emmc driver.
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- Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
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- Enhanced the CPU operations framework to allow power handlers to be
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registered on per-level basis. This enables support for future CPUs that
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have multiple threads which might need powering down individually.
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- Updated register initialisation to prevent unexpected behaviour:
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- Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
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unexpected traps into the higher exception levels and disable secure
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self-hosted debug. Additionally, secure privileged external debug on
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Juno is disabled by programming the appropriate Juno SoC registers.
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- EL2 and EL3 configurable controls are initialised to avoid unexpected
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traps in the higher exception levels.
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- Essential control registers are fully initialised on EL3 start-up, when
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initialising the non-secure and secure context structures and when
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preparing to leave EL3 for a lower EL. This gives better alignement with
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the ARM ARM which states that software must initialise RES0 and RES1
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fields with 0 / 1.
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- Enhanced PSCI support:
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- Introduced new platform interfaces that decouple PSCI stat residency
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calculation from PMF, enabling platforms to use alternative methods of
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capturing timestamps.
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- PSCI stat accounting performed for retention/standby states when
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requested at multiple power levels.
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- Simplified fiptool to have a single linked list of image descriptors.
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- For the TSP, resolved corruption of pre-empted secure context by aborting any
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pre-empted SMC during PSCI power management requests.
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Issues resolved since last release
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==================================
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- ARM TF can be built with the latest mbed TLS version (v2.4.2). The earlier
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version 2.3.0 cannot be used due to build warnings that the ARM TF build
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system interprets as errors.
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- TBBR, including the Firmware Update feature is now supported on FVP
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platforms when running Trusted Firmware in AArch32 state.
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- The version of the AEMv8 Base FVP used in this release has resolved the issue
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of the model executing a reset instead of terminating in response to a
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shutdown request using the PSCI SYSTEM_OFF API.
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Known Issues
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============
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- Building TF with compiler optimisations disabled (-O0) fails.
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- Trusted Board Boot currently does not work on Juno when running Trusted
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Firmware in AArch32 execution state due to error when loading the sp_min to
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memory becasue of lack of free space available. See `tf-issue#501`_ for more
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details.
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- The errata workaround for A53 errata 843419 is only available from binutils
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2.26 and is not present in GCC4.9. If this errata is applicable to the
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platform, please use GCC compiler version of at least 5.0. See `PR#1002`_ for
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more details.
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ARM Trusted Firmware - version 1.3
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==================================
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@ -1088,3 +1378,5 @@ releases of the ARM Trusted Firmware.
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.. _TF wiki on GitHub: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
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.. _Authentication Framework: auth-framework.rst
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.. _OP-TEE Dispatcher: optee-dispatcher.rst
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.. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
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.. _PR#1002: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
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