From 12f06f1c0e1962a5d6a0239581574ce8ea456a62 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Tue, 14 Feb 2017 18:02:04 -0800 Subject: [PATCH 1/7] Tegra194: Enable system suspend This patch does the following: 1. Populate the cstate info corresponding to system suspend and communicate it to the MCE 2. Ask for MCE's acknowledgement for entering system suspend and instruct MCE to get inside system suspend once permitted Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506 Signed-off-by: Tejal Kudav Signed-off-by: Vignesh Radhakrishnan --- .../tegra/soc/t194/plat_psci_handlers.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index b7a6c4f8d..495a2c40d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -18,6 +18,7 @@ #include #include #include +#include extern void prepare_core_pwr_dwn(void); @@ -93,6 +94,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) uint64_t smmu_ctx_base; #endif uint32_t val; + mce_cstate_info_t cstate_info = { 0 }; /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; @@ -131,7 +133,24 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif - /* Instruct the MCE to enter system suspend state */ + /* Prepare for system suspend */ + cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; + cstate_info.system = TEGRA_NVG_SYSTEM_SC7; + cstate_info.system_state_force = 1; + cstate_info.update_wake_mask = 1; + mce_update_cstate_info(&cstate_info); + + do { + val = mce_command_handler( + MCE_CMD_IS_SC7_ALLOWED, + TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0); + } while (val == 0); + + /* Instruct the MCE to enter system suspend state */ + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); } return PSCI_E_SUCCESS; From 5da8ec562ecee9d70c13e0d62d17da6780be01e2 Mon Sep 17 00:00:00 2001 From: Vignesh Radhakrishnan Date: Mon, 10 Apr 2017 15:07:39 -0700 Subject: [PATCH 2/7] Tegra194: skip notifying MCE in fake system suspend - In pre-silicon platforms, MCE might not be ready to support system suspend(SC7) - Thus, in fake system suspend mode, bypass waiting for MCE's acknowledgment to enter system suspend Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6 Signed-off-by: Vignesh Radhakrishnan --- .../tegra/soc/t194/plat_psci_handlers.c | 38 +++++++++++-------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 495a2c40d..e53d5946e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -22,6 +22,8 @@ extern void prepare_core_pwr_dwn(void); +extern uint8_t tegra_fake_system_suspend; + #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM extern void tegra186_cpu_reset_handler(void); extern uint32_t __tegra186_cpu_reset_handler_data, @@ -133,24 +135,28 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) tegra_smmu_save_context(0); #endif - /* Prepare for system suspend */ - cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; - cstate_info.system = TEGRA_NVG_SYSTEM_SC7; - cstate_info.system_state_force = 1; - cstate_info.update_wake_mask = 1; - mce_update_cstate_info(&cstate_info); + if (tegra_fake_system_suspend == 0U) { - do { - val = mce_command_handler( - MCE_CMD_IS_SC7_ALLOWED, - TEGRA_NVG_CORE_C7, - MCE_CORE_SLEEP_TIME_INFINITE, - 0); - } while (val == 0); + /* Prepare for system suspend */ + cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6; + cstate_info.system = TEGRA_NVG_SYSTEM_SC7; + cstate_info.system_state_force = 1; + cstate_info.update_wake_mask = 1; - /* Instruct the MCE to enter system suspend state */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + mce_update_cstate_info(&cstate_info); + + do { + val = mce_command_handler( + MCE_CMD_IS_SC7_ALLOWED, + TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0); + } while (val == 0); + + /* Instruct the MCE to enter system suspend state */ + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, + TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + } } return PSCI_E_SUCCESS; From 2fdd9ae6c7b79b2e667a743eb3d781ea0e7f1da0 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 26 Apr 2017 08:57:27 -0700 Subject: [PATCH 3/7] Tegra194: add macros to read GPU reset status This patch adds macros to check the GPU reset status bit, before resizing the VideoMem region. Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t194/tegra_def.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a1b70db9f..79d776f55 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -232,5 +232,7 @@ * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE 0x200000000 +#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL +#define GPU_RESET_BIT (1UL << 0) #endif /* __TEGRA_DEF_H__ */ From 73dad7f9c70eb1a867791efefc077e80cef279e5 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Fri, 28 Apr 2017 13:52:58 +0800 Subject: [PATCH 4/7] Tegra194: mce: fix function declaration conflicts To fix MISRA defects, remove union in t186 MCE drivers this driver should compatible with that. Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index f13643fc0..0a6515e1c 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -25,7 +25,7 @@ /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ -int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, +int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2) { uint64_t ret64 = 0, arg3, arg4, arg5; @@ -161,7 +161,7 @@ int32_t mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, break; default: - ERROR("unknown MCE command (%lld)\n", cmd); + ERROR("unknown MCE command (%llu)\n", cmd); ret = EINVAL; break; } @@ -196,7 +196,7 @@ int32_t mce_update_gsc_tzram(void) /******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ -void mce_update_cstate_info(mce_cstate_info_t *cstate) +void mce_update_cstate_info(const mce_cstate_info_t *cstate) { /* issue the UPDATE_CSTATE_INFO request */ nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, From 42de03848f61c79f4f1aeb2ce91df1eac59fa3fb Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 28 Apr 2017 08:45:53 -0700 Subject: [PATCH 5/7] Tegra194: implement handler to retrieve power domain tree This patch implements the platform handler to return the pointer to the power domain tree. Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_setup.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 3424d1928..7ca65dd06 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -45,6 +45,14 @@ const unsigned char tegra_power_domain_tree_desc[] = { PLATFORM_MAX_CPUS_PER_CLUSTER }; +/******************************************************************************* + * This function returns the Tegra default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return tegra_power_domain_tree_desc; +} + /* * Table of regions to map using the MMU. */ From 2e446f50bde561913276ef6d930a20dfeadf416d Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 28 Apr 2017 18:15:09 -0700 Subject: [PATCH 6/7] Tegra194: sip_calls: mark unused parameter as const This patch marks the unused parameter 'cookie', to the plat_sip_handler() function, as const to fix an issue flagged by the MISRA scan. Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index cb57c9b61..eaad73a40 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -51,7 +51,7 @@ int plat_sip_handler(uint32_t smc_fid, uint64_t x2, uint64_t x3, uint64_t x4, - void *cookie, + const void *cookie, void *handle, uint64_t flags) { From d191573e6ae616adb3b6ce2404a4cff9bf4c0052 Mon Sep 17 00:00:00 2001 From: Harvey Hsieh Date: Wed, 23 Nov 2016 19:15:02 +0800 Subject: [PATCH 7/7] Tegra194: remove L2 ECC parity protection setting This patch removes the code to enable L2 ECC parity protection bit, as Tegra194 does not have any Cortex-A57 CPUs. Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af Signed-off-by: Harvey Hsieh --- plat/nvidia/tegra/soc/t194/plat_setup.c | 37 ------------------------- 1 file changed, 37 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 7ca65dd06..a3a2515ca 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -25,9 +25,6 @@ #include #include -DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) -extern uint64_t tegra_enable_l2_ecc_parity_prot; - /******************************************************************************* * The Tegra power domain tree has a single system level power domain i.e. a * single root node. The first entry in the power domain descriptor specifies @@ -145,49 +142,15 @@ uint32_t plat_get_console_from_id(int id) return tegra186_uart_addresses[id]; } -/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ -#define TEGRA186_VER_A02P 0x1201 - /******************************************************************************* * Handler for early platform setup ******************************************************************************/ void plat_early_platform_setup(void) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; - uint32_t chip_subrev, val; /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); - /* - * Enable ECC and Parity Protection for Cortex-A57 CPUs - * for Tegra A02p SKUs - */ - if (impl != DENVER_IMPL) { - - /* get the major, minor and sub-version values */ - chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & - SUBREVISION_MASK; - - /* prepare chip version number */ - val = (tegra_get_chipid_major() << 12) | - (tegra_get_chipid_minor() << 8) | - chip_subrev; - - /* enable L2 ECC for Tegra186 A02P and beyond */ - if (val >= TEGRA186_VER_A02P) { - - val = read_l2ctlr_el1(); - val |= L2_ECC_PARITY_PROTECTION_BIT; - write_l2ctlr_el1(val); - - /* - * Set the flag to enable ECC/Parity Protection - * when we exit System Suspend or Cluster Powerdn - */ - tegra_enable_l2_ecc_parity_prot = 1; - } - } } /* Secure IRQs for Tegra186 */