rockchip/rk3399: Move DRAM restore to PMUSRAM
This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Derek Basehore
Caesar Wang
parent
c82eef6ce5
commit
af27fb89a9
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@ -10,7 +10,7 @@
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#include <soc.h>
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#include <rk3399_def.h>
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__sramdata struct rk3399_sdram_params sdram_config;
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__pmusramdata struct rk3399_sdram_params sdram_config;
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void dram_init(void)
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{
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@ -45,7 +45,8 @@
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/*
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* Copy @num registers from @src to @dst
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*/
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__sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num)
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static __pmusramfunc void sram_regcpy(uintptr_t dst, uintptr_t src,
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uint32_t num)
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{
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while (num--) {
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mmio_write_32(dst, mmio_read_32(src));
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@ -54,7 +55,21 @@ __sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num)
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}
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}
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static __sramfunc uint32_t sram_get_timer_value(void)
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/*
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* Copy @num registers from @src to @dst
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* This is intentionally a copy of the sram_regcpy function. PMUSRAM functions
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* cannot be called from code running in DRAM.
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*/
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static void dram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num)
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{
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while (num--) {
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mmio_write_32(dst, mmio_read_32(src));
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dst += sizeof(uint32_t);
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src += sizeof(uint32_t);
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}
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}
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static __pmusramfunc uint32_t sram_get_timer_value(void)
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{
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/*
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* Generic delay timer implementation expects the timer to be a down
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@ -64,7 +79,7 @@ static __sramfunc uint32_t sram_get_timer_value(void)
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return (uint32_t)(~read_cntpct_el0());
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}
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static __sramfunc void sram_udelay(uint32_t usec)
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static __pmusramfunc void sram_udelay(uint32_t usec)
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{
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uint32_t start, cnt, delta, delta_us;
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@ -81,7 +96,7 @@ static __sramfunc void sram_udelay(uint32_t usec)
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} while (delta_us < usec);
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}
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static __sramfunc void configure_sgrf(void)
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static __pmusramfunc void configure_sgrf(void)
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{
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/*
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* SGRF_DDR_RGN_DPLL_CLK and SGRF_DDR_RGN_RTC_CLK:
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@ -98,7 +113,7 @@ static __sramfunc void configure_sgrf(void)
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SGRF_DDR_RGN_BYPS);
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}
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static __sramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl,
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static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl,
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uint32_t phy)
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{
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channel &= 0x1;
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@ -109,7 +124,7 @@ static __sramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl,
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CRU_SFTRST_DDR_PHY(channel, phy));
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}
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static __sramfunc void phy_pctrl_reset(uint32_t ch)
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static __pmusramfunc void phy_pctrl_reset(uint32_t ch)
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{
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rkclk_ddr_reset(ch, 1, 1);
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sram_udelay(10);
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@ -119,7 +134,7 @@ static __sramfunc void phy_pctrl_reset(uint32_t ch)
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sram_udelay(10);
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}
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static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
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static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
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{
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uint32_t byte;
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@ -129,14 +144,15 @@ static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
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rank << 24);
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}
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static __sramfunc void select_per_cs_training_index(uint32_t ch, uint32_t rank)
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static __pmusramfunc void select_per_cs_training_index(uint32_t ch,
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uint32_t rank)
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{
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/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
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if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1)
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set_cs_training_index(ch, rank);
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}
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static void override_write_leveling_value(uint32_t ch)
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static __pmusramfunc void override_write_leveling_value(uint32_t ch)
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{
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uint32_t byte;
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@ -156,7 +172,7 @@ static void override_write_leveling_value(uint32_t ch)
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mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8);
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}
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static __sramfunc int data_training(uint32_t ch,
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static __pmusramfunc int data_training(uint32_t ch,
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struct rk3399_sdram_params *sdram_params,
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uint32_t training_flag)
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{
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@ -401,7 +417,8 @@ static __sramfunc int data_training(uint32_t ch,
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return 0;
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}
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static __sramfunc void set_ddrconfig(struct rk3399_sdram_params *sdram_params,
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static __pmusramfunc void set_ddrconfig(
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struct rk3399_sdram_params *sdram_params,
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unsigned char channel, uint32_t ddrconfig)
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{
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/* only need to set ddrconfig */
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@ -423,7 +440,8 @@ static __sramfunc void set_ddrconfig(struct rk3399_sdram_params *sdram_params,
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((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8));
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}
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static __sramfunc void dram_all_config(struct rk3399_sdram_params *sdram_params)
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static __pmusramfunc void dram_all_config(
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struct rk3399_sdram_params *sdram_params)
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{
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unsigned int i;
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@ -459,7 +477,7 @@ static __sramfunc void dram_all_config(struct rk3399_sdram_params *sdram_params)
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mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3);
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}
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static __sramfunc void pctl_cfg(uint32_t ch,
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static __pmusramfunc void pctl_cfg(uint32_t ch,
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struct rk3399_sdram_params *sdram_params)
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{
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const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl;
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@ -516,7 +534,7 @@ static __sramfunc void pctl_cfg(uint32_t ch,
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(uintptr_t)&phy_regs->phy512[i][0], 38);
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}
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static __sramfunc int dram_switch_to_next_index(
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static __pmusramfunc int dram_switch_to_next_index(
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struct rk3399_sdram_params *sdram_params)
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{
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uint32_t ch, ch_count;
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@ -551,7 +569,7 @@ static __sramfunc int dram_switch_to_next_index(
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* Needs to be done for both channels at once in case of a shared reset signal
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* between channels.
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*/
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static __sramfunc int pctl_start(uint32_t channel_mask,
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static __pmusramfunc int pctl_start(uint32_t channel_mask,
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struct rk3399_sdram_params *sdram_params)
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{
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uint32_t count;
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@ -644,26 +662,26 @@ void dmc_save(void)
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0x7) != 0) ? 1 : 0;
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/* copy the registers CTL PI and PHY */
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sram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM);
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dram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM);
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/* mask DENALI_CTL_00_DATA.START, only copy here, will trigger later */
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params_ctl[0] &= ~(0x1 << 0);
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sram_regcpy((uintptr_t)¶ms_pi[0], PI_REG(0, 0),
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dram_regcpy((uintptr_t)¶ms_pi[0], PI_REG(0, 0),
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PI_REG_NUM);
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/* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/
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params_pi[0] &= ~(0x1 << 0);
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for (i = 0; i < 4; i++)
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sram_regcpy((uintptr_t)&phy_regs->phy0[i][0],
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dram_regcpy((uintptr_t)&phy_regs->phy0[i][0],
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PHY_REG(0, 128 * i), 91);
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for (i = 0; i < 3; i++)
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sram_regcpy((uintptr_t)&phy_regs->phy512[i][0],
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dram_regcpy((uintptr_t)&phy_regs->phy512[i][0],
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PHY_REG(0, 512 + 128 * i), 38);
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sram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63);
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dram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63);
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for (ch = 0; ch < sdram_params->num_channels; ch++) {
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for (byte = 0; byte < 4; byte++)
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@ -678,7 +696,7 @@ void dmc_save(void)
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phy_regs->phy896[0] &= ~(0x3 << 8);
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}
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__sramfunc void dmc_restore(void)
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__pmusramfunc void dmc_restore(void)
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{
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struct rk3399_sdram_params *sdram_params = &sdram_config;
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uint32_t channel_mask = 0;
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@ -20,7 +20,6 @@
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#define PI_FULL_TRAINING (0xff)
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void dmc_save(void);
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__sramfunc void dmc_restore(void);
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__sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num);
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__pmusramfunc void dmc_restore(void);
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#endif /* __DRAM_H__ */
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