From afa0b1a82a404c616da2da8f52cdcd587938955f Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 6 Aug 2020 10:21:54 +0800 Subject: [PATCH] feat(intel): create source file for firewall configuration Move codes that previously were part of system_manager driver into firewall driver which are more appropriate based on their functionalities. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I35e9d792f35ee7491c2f306781417a0c8faae3fd Signed-off-by: Jit Loon Lim --- plat/intel/soc/agilex/platform.mk | 2 +- plat/intel/soc/common/include/socfpga_noc.h | 14 +++++++++++++- .../soc/common/include/socfpga_system_manager.h | 11 ----------- ...socfpga_system_manager.c => socfpga_firewall.c} | 11 +++++++++-- plat/intel/soc/stratix10/platform.mk | 2 +- 5 files changed, 24 insertions(+), 16 deletions(-) rename plat/intel/soc/common/soc/{socfpga_system_manager.c => socfpga_firewall.c} (96%) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 10a3eec42..17bfbdd8e 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -48,10 +48,10 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ + plat/intel/soc/common/soc/socfpga_firewall.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ - plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h index 66d0ee72a..ecf5bcc51 100644 --- a/plat/intel/soc/common/include/socfpga_noc.h +++ b/plat/intel/soc/common/include/socfpga_noc.h @@ -8,6 +8,13 @@ #define SOCFPGA_NOC_H /* Macros */ +#define SCR_AXI_AP_MASK BIT(24) +#define SCR_FPGA2SOC_MASK BIT(16) +#define SCR_MPU_MASK BIT(0) +#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ + | SCR_MPU_MASK) +#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 + #define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) @@ -78,5 +85,10 @@ #define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) #define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) -#endif +/* Function Definitions */ +void enable_ns_peripheral_access(void); +void enable_ns_bridge_access(void); +void enable_ns_ocram_access(void); + +#endif diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index b037cc61c..a77734d17 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -42,13 +42,6 @@ #define IDLE_DATA_SOC2FPGA BIT(4) #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) -#define SCR_AXI_AP_MASK BIT(24) -#define SCR_FPGA2SOC_MASK BIT(16) -#define SCR_MPU_MASK BIT(0) -#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ - | SCR_MPU_MASK) -#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 - #define SYSMGR_ECC_OCRAM_MASK BIT(1) #define SYSMGR_ECC_DDR0_MASK BIT(16) #define SYSMGR_ECC_DDR1_MASK BIT(17) @@ -58,8 +51,4 @@ #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + (SOCFPGA_SYSMGR_##_reg)) - -void enable_ns_peripheral_access(void); -void enable_ns_bridge_access(void); - #endif /* SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_firewall.c similarity index 96% rename from plat/intel/soc/common/soc/socfpga_system_manager.c rename to plat/intel/soc/common/soc/socfpga_firewall.c index ee7c7846d..b6cf32190 100644 --- a/plat/intel/soc/common/soc/socfpga_system_manager.c +++ b/plat/intel/soc/common/soc/socfpga_firewall.c @@ -8,6 +8,7 @@ #include #include "socfpga_noc.h" +#include "socfpga_plat_def.h" #include "socfpga_system_manager.h" void enable_nonsecure_access(void) @@ -93,12 +94,18 @@ void enable_ns_peripheral_access(void) mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + enable_ns_ocram_access(); + mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); +#endif + +} + +void enable_ns_ocram_access(void) +{ mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0), SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); -#endif - } void enable_ns_bridge_access(void) diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index d9d88d418..21dc2d44c 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -47,10 +47,10 @@ BL2_SOURCES += \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ + plat/intel/soc/common/soc/socfpga_firewall.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c \ - plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c