bl2-el3: Add BL2_EL3 image
This patch enables BL2 to execute at the highest exception level without any dependancy on TF BL1. This enables platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This is not currently possible because BL2 executes at S-EL1 and cannot jump straight to EL3. Change-Id: Ief1efca4598560b1b8c8e61fbe26d1f44e929d69 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
This commit is contained in:
Roberto Vargas
parent
34c2b9c2f1
commit
b1d27b484f
2
Makefile
2
Makefile
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@ -500,6 +500,7 @@ $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
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$(eval $(call assert_boolean,USE_COHERENT_MEM))
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$(eval $(call assert_boolean,USE_TBBR_DEFS))
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$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
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$(eval $(call assert_boolean,BL2_AT_EL3))
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$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
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$(eval $(call assert_numeric,ARM_ARCH_MINOR))
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@ -543,6 +544,7 @@ $(eval $(call add_define,TRUSTED_BOARD_BOOT))
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$(eval $(call add_define,USE_COHERENT_MEM))
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$(eval $(call add_define,USE_TBBR_DEFS))
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$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
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$(eval $(call add_define,BL2_AT_EL3))
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# Define the EL3_PAYLOAD_BASE flag only if it is provided.
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ifdef EL3_PAYLOAD_BASE
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@ -0,0 +1,84 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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.globl bl2_run_next_image
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov r9, r0
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mov r10, r1
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mov r11, r2
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mov r12, r3
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_vector_table
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/*
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* Restore parameters of boot rom
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*/
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mov r0, r9
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mov r1, r10
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mov r2, r11
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mov r3, r12
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bl bl2_el3_early_platform_setup
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bl bl2_el3_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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func bl2_run_next_image
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mov r8,r0
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/*
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* MMU needs to be disabled because both BL2 and BL32 execute
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* in PL1, and therefore share the same address space.
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* BL32 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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mov r0, r8
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bl bl2_el3_plat_prepare_exit
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr, r1
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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eret
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endfunc bl2_run_next_image
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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.globl bl2_vector_table
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vector_base bl2_vector_table
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b bl2_entrypoint
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b report_exception /* Undef */
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b report_exception /* SVC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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@ -0,0 +1,77 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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.globl bl2_vector_table
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.globl bl2_el3_run_image
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.globl bl2_run_next_image
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_el3_exceptions
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/*
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* Restore parameters of boot rom
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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bl bl2_el3_early_platform_setup
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bl bl2_el3_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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func bl2_run_next_image
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mov x20,x0
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/*
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* MMU needs to be disabled because both BL2 and BL31 execute
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* in EL3, and therefore share the same address space.
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* BL31 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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bl bl2_el3_plat_prepare_exit
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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eret
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endfunc bl2_run_next_image
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@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1.h>
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#include <bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL2.
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* -----------------------------------------------------------------------------
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*/
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.globl bl2_el3_exceptions
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vector_base bl2_el3_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SynchronousExceptionSP0
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size IrqSP0
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size FiqSP0
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SynchronousExceptionSPx
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size IrqSPx
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size FiqSPx
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SynchronousExceptionA64
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size IrqA64
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size FiqA64
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SynchronousExceptionA32
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size IrqA32
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size FiqA32
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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check_vector_size SErrorA32
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12
bl2/bl2.mk
12
bl2/bl2.mk
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@ -5,7 +5,6 @@
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#
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BL2_SOURCES += bl2/bl2_main.c \
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bl2/${ARCH}/bl2_entrypoint.S \
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bl2/${ARCH}/bl2_arch_setup.c \
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lib/locks/exclusive/${ARCH}/spinlock.S \
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plat/common/${ARCH}/platform_up_stack.S
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@ -20,4 +19,15 @@ else
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BL2_SOURCES += bl2/bl2_image_load.c
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endif
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ifeq (${BL2_AT_EL3},0)
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BL2_SOURCES += bl2/${ARCH}/bl2_entrypoint.S
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BL2_LINKERFILE := bl2/bl2.ld.S
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else
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BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \
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bl2/${ARCH}/bl2_el3_exceptions.S \
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plat/common/plat_bl2_el3_common.c \
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lib/cpus/${ARCH}/cpu_helpers.S \
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lib/cpus/errata_report.c
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BL2_LINKERFILE := bl2/bl2_el3.ld.S
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endif
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@ -0,0 +1,175 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
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}
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SECTIONS
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{
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. = BL2_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL2_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl2_el3_entrypoint.o(.text*)
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*(.text*)
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*(.vectors)
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. = NEXT(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PARSER_LIB_DESCS_START__ = .;
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KEEP(*(.img_parser_lib_descs))
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__PARSER_LIB_DESCS_END__ = .;
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/*
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* Ensure 8-byte alignment for cpu_ops so that its fields are also
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* aligned. Also ensure cpu_ops inclusion.
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*/
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. = ALIGN(8);
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__CPU_OPS_START__ = .;
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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. = NEXT(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else
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ro . : {
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__RO_START__ = .;
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*bl2_el3_entrypoint.o(.text*)
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*(.text*)
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*(.rodata*)
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/*
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* Ensure 8-byte alignment for cpu_ops so that its fields are also
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* aligned. Also ensure cpu_ops inclusion.
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*/
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. = ALIGN(8);
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__CPU_OPS_START__ = .;
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PARSER_LIB_DESCS_START__ = .;
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KEEP(*(.img_parser_lib_descs))
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__PARSER_LIB_DESCS_END__ = .;
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as
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* read-only, executable. No RW data from the next section must
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* creep in. Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif
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ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
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"cpu_ops not defined for this platform.")
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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/*
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* .data must be placed at a lower address than the stacks if the stack
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* protector is enabled. Alternatively, the .data.stack_protector_canary
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* section can be placed independently of the main .data section.
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*/
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.data . : {
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__DATA_START__ = .;
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*(.data*)
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__DATA_END__ = .;
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} >RAM
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address should be 16-byte aligned for better performance of the
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* zero-initialization code.
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*/
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.bss : ALIGN(16) {
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__BSS_START__ = .;
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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__BSS_END__ = .;
|
||||
} >RAM
|
||||
|
||||
/*
|
||||
* The xlat_table section is for full, aligned page tables (4K).
|
||||
* Removing them from .bss avoids forcing 4K alignment on
|
||||
* the .bss section and eliminates the unnecessary zero init
|
||||
*/
|
||||
xlat_table (NOLOAD) : {
|
||||
*(xlat_table)
|
||||
} >RAM
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* The base address of the coherent memory section must be page-aligned (4K)
|
||||
* to guarantee that the coherent data are stored on their own pages and
|
||||
* are not mixed with normal data. This is required to set up the correct
|
||||
* memory attributes for the coherent data page tables.
|
||||
*/
|
||||
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||
__COHERENT_RAM_START__ = .;
|
||||
*(tzfw_coherent_mem)
|
||||
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||
/*
|
||||
* Memory page(s) mapped to this section will be marked
|
||||
* as device memory. No other unexpected data must creep in.
|
||||
* Ensure the rest of the current memory page is unused.
|
||||
*/
|
||||
. = NEXT(PAGE_SIZE);
|
||||
__COHERENT_RAM_END__ = .;
|
||||
} >RAM
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define a linker symbol to mark end of the RW memory area for this
|
||||
* image.
|
||||
*/
|
||||
__RW_END__ = .;
|
||||
__BL2_END__ = .;
|
||||
|
||||
__BSS_SIZE__ = SIZEOF(.bss);
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||
#endif
|
||||
|
||||
ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
|
||||
}
|
||||
|
|
@ -13,6 +13,11 @@
|
|||
#include <platform.h>
|
||||
#include "bl2_private.h"
|
||||
|
||||
#ifdef AARCH32
|
||||
#define NEXT_IMAGE "BL32"
|
||||
#else
|
||||
#define NEXT_IMAGE "BL31"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* The only thing to do in BL2 is to load further images and pass control to
|
||||
|
|
@ -49,6 +54,8 @@ void bl2_main(void)
|
|||
disable_mmu_icache_secure();
|
||||
#endif /* AARCH32 */
|
||||
|
||||
|
||||
#if !BL2_AT_EL3
|
||||
console_flush();
|
||||
|
||||
/*
|
||||
|
|
@ -57,4 +64,11 @@ void bl2_main(void)
|
|||
* be passed to next BL image as an argument.
|
||||
*/
|
||||
smc(BL1_SMC_RUN_IMAGE, (unsigned long)next_bl_ep_info, 0, 0, 0, 0, 0, 0);
|
||||
#else
|
||||
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
|
||||
print_entry_point_info(next_bl_ep_info);
|
||||
console_flush();
|
||||
|
||||
bl2_run_next_image(next_bl_ep_info);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -17,5 +17,6 @@ struct entry_point_info;
|
|||
*****************************************/
|
||||
void bl2_arch_setup(void);
|
||||
struct entry_point_info *bl2_load_images(void);
|
||||
void bl2_run_next_image(const entry_point_info_t *bl_ep_info);
|
||||
|
||||
#endif /* __BL2_PRIVATE_H__ */
|
||||
|
|
|
|||
|
|
@ -260,9 +260,9 @@
|
|||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
.if \_init_c_runtime
|
||||
#ifdef IMAGE_BL32
|
||||
#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
/* -----------------------------------------------------------------
|
||||
* Invalidate the RW memory used by the BL32 (SP_MIN) image. This
|
||||
* Invalidate the RW memory used by the image. This
|
||||
* includes the data and NOBITS sections. This is done to
|
||||
* safeguard against possible corruption of this memory by
|
||||
* dirty cache lines in a system cache as a result of use by
|
||||
|
|
@ -273,7 +273,7 @@
|
|||
ldr r1, =__RW_END__
|
||||
sub r1, r1, r0
|
||||
bl inv_dcache_range
|
||||
#endif /* IMAGE_BL32 */
|
||||
#endif
|
||||
|
||||
ldr r0, =__BSS_START__
|
||||
ldr r1, =__BSS_SIZE__
|
||||
|
|
|
|||
|
|
@ -269,7 +269,7 @@
|
|||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
.if \_init_c_runtime
|
||||
#ifdef IMAGE_BL31
|
||||
#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
/* -------------------------------------------------------------
|
||||
* Invalidate the RW memory used by the BL31 image. This
|
||||
* includes the data and NOBITS sections. This is done to
|
||||
|
|
@ -282,7 +282,7 @@
|
|||
adr x1, __RW_END__
|
||||
sub x1, x1, x0
|
||||
bl inv_dcache_range
|
||||
#endif /* IMAGE_BL31 */
|
||||
#endif
|
||||
|
||||
ldr x0, =__BSS_START__
|
||||
ldr x1, =__BSS_SIZE__
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@
|
|||
#include <arch.h>
|
||||
#include <errata_report.h>
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
#define IMAGE_AT_EL3
|
||||
#endif
|
||||
|
||||
#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
|
||||
(MIDR_PN_MASK << MIDR_PN_SHIFT)
|
||||
|
||||
|
|
@ -38,7 +42,7 @@
|
|||
CPU_MIDR: /* cpu_ops midr */
|
||||
.space 4
|
||||
/* Reset fn is needed during reset */
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
CPU_RESET_FUNC: /* cpu_ops reset_func */
|
||||
.space 4
|
||||
#endif
|
||||
|
|
@ -54,7 +58,7 @@ CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
|
|||
#if REPORT_ERRATA
|
||||
CPU_ERRATA_FUNC: /* CPU errata status printing function */
|
||||
.space 4
|
||||
#ifdef IMAGE_BL32
|
||||
#if defined(IMAGE_BL32)
|
||||
CPU_ERRATA_LOCK:
|
||||
.space 4
|
||||
CPU_ERRATA_PRINTED:
|
||||
|
|
@ -120,7 +124,7 @@ CPU_OPS_SIZE = .
|
|||
.align 2
|
||||
.type cpu_ops_\_name, %object
|
||||
.word \_midr
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.word \_resetfunc
|
||||
#endif
|
||||
#ifdef IMAGE_BL32
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@
|
|||
/* Word size for 64-bit CPUs */
|
||||
#define CPU_WORD_SIZE 8
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
#define IMAGE_AT_EL3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Whether errata status needs reporting. Errata status is printed in debug
|
||||
* builds for both BL1 and BL31 images.
|
||||
|
|
@ -38,7 +42,7 @@
|
|||
CPU_MIDR: /* cpu_ops midr */
|
||||
.space 8
|
||||
/* Reset fn is needed in BL at reset vector */
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
CPU_RESET_FUNC: /* cpu_ops reset_func */
|
||||
.space 8
|
||||
#endif
|
||||
|
|
@ -54,7 +58,7 @@ CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
|
|||
#if REPORT_ERRATA
|
||||
CPU_ERRATA_FUNC:
|
||||
.space 8
|
||||
#ifdef IMAGE_BL31
|
||||
#if defined(IMAGE_BL31)
|
||||
CPU_ERRATA_LOCK:
|
||||
.space 8
|
||||
CPU_ERRATA_PRINTED:
|
||||
|
|
@ -124,7 +128,7 @@ CPU_OPS_SIZE = .
|
|||
.align 3
|
||||
.type cpu_ops_\_name, %object
|
||||
.quad \_midr
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.quad \_resetfunc
|
||||
#endif
|
||||
#ifdef IMAGE_BL31
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ struct xlat_ctx {
|
|||
* This IMAGE_EL macro must not to be used outside the library, and it is only
|
||||
* used in AArch64.
|
||||
*/
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
# define IMAGE_EL 3
|
||||
# define IMAGE_XLAT_DEFAULT_REGIME EL3_REGIME
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -235,6 +235,21 @@ void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
|
|||
* Optional BL2 functions (may be overridden)
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Mandatory BL2 at EL3 functions: Must be implemented if BL2_AT_EL3 image is
|
||||
* supported
|
||||
******************************************************************************/
|
||||
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3);
|
||||
void bl2_el3_plat_arch_setup(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Optional BL2 at EL3 functions (may be overridden)
|
||||
******************************************************************************/
|
||||
void bl2_el3_plat_prepare_exit(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Mandatory BL2U functions.
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#include <cpu_data.h>
|
||||
#include <cpu_macros.S>
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
/*
|
||||
* The reset handler common to all platforms. After a matching
|
||||
* cpu_ops structure entry is found, the correponding reset_handler
|
||||
|
|
@ -42,7 +42,7 @@ func reset_handler
|
|||
bx lr
|
||||
endfunc reset_handler
|
||||
|
||||
#endif /* IMAGE_BL1 || IMAGE_BL32 */
|
||||
#endif
|
||||
|
||||
#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#ifdef IMAGE_BL31
|
||||
#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
#include <cpu_data.h>
|
||||
#endif
|
||||
#include <cpu_macros.S>
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
#include <errata_report.h>
|
||||
|
||||
/* Reset fn is needed in BL at reset vector */
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
/*
|
||||
* The reset handler common to all platforms. After a matching
|
||||
* cpu_ops structure entry is found, the correponding reset_handler
|
||||
|
|
@ -47,7 +47,7 @@ func reset_handler
|
|||
ret
|
||||
endfunc reset_handler
|
||||
|
||||
#endif /* IMAGE_BL1 || IMAGE_BL31 */
|
||||
#endif
|
||||
|
||||
#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
# define BL_STRING "BL31"
|
||||
#elif defined(AARCH32) && defined(IMAGE_BL32)
|
||||
# define BL_STRING "BL32"
|
||||
#elif defined(IMAGE_BL2) && BL2_AT_EL3
|
||||
# define BL_STRING "BL2"
|
||||
#else
|
||||
# error This image should not be printing errata status
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,9 @@ ARM_GIC_ARCH := 2
|
|||
# Base commit to perform code check on
|
||||
BASE_COMMIT := origin/master
|
||||
|
||||
# Execute BL2 at EL3
|
||||
BL2_AT_EL3 := 0
|
||||
|
||||
# By default, consider that the platform may release several CPUs out of reset.
|
||||
# The platform Makefile is free to override this value.
|
||||
COLD_BOOT_SINGLE_CPU := 0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/*
|
||||
* The following platform functions are weakly defined. They
|
||||
* are default implementations that allow BL2 to compile in
|
||||
* absence of real definitions. The Platforms may override
|
||||
* with more complex definitions.
|
||||
*/
|
||||
#pragma weak bl2_el3_plat_prepare_exit
|
||||
|
||||
void bl2_el3_plat_prepare_exit(void)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue