crypto: stm32_hash: Add HASH driver
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdint.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32_hash.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#define DT_HASH_COMPAT "st,stm32f756-hash"
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#define HASH_CR 0x00U
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#define HASH_DIN 0x04U
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#define HASH_STR 0x08U
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#define HASH_SR 0x24U
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#define HASH_HREG(x) (0x310U + ((x) * 0x04U))
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/* Control Register */
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#define HASH_CR_INIT BIT(2)
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#define HASH_CR_DATATYPE_SHIFT U(4)
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#define HASH_CR_ALGO_SHA1 0x0U
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#define HASH_CR_ALGO_MD5 BIT(7)
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#define HASH_CR_ALGO_SHA224 BIT(18)
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#define HASH_CR_ALGO_SHA256 (BIT(18) | BIT(7))
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/* Status Flags */
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#define HASH_SR_DCIS BIT(1)
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#define HASH_SR_BUSY BIT(3)
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/* STR Register */
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#define HASH_STR_NBLW_MASK GENMASK(4, 0)
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#define HASH_STR_DCAL BIT(8)
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#define MD5_DIGEST_SIZE 16U
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#define SHA1_DIGEST_SIZE 20U
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#define SHA224_DIGEST_SIZE 28U
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#define SHA256_DIGEST_SIZE 32U
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#define HASH_TIMEOUT_US 10000U
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enum stm32_hash_data_format {
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HASH_DATA_32_BITS,
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HASH_DATA_16_BITS,
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HASH_DATA_8_BITS,
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HASH_DATA_1_BIT
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};
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struct stm32_hash_instance {
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uintptr_t base;
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unsigned int clock;
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size_t digest_size;
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};
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struct stm32_hash_remain {
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uint32_t buffer;
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size_t length;
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};
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/* Expect a single HASH peripheral */
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static struct stm32_hash_instance stm32_hash;
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static struct stm32_hash_remain stm32_remain;
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static uintptr_t hash_base(void)
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{
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return stm32_hash.base;
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}
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static int hash_wait_busy(void)
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{
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uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
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while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_BUSY) != 0U) {
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if (timeout_elapsed(timeout)) {
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ERROR("%s: busy timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int hash_wait_computation(void)
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{
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uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
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while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_DCIS) == 0U) {
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if (timeout_elapsed(timeout)) {
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ERROR("%s: busy timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int hash_write_data(uint32_t data)
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{
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int ret;
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ret = hash_wait_busy();
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if (ret != 0) {
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return ret;
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}
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mmio_write_32(hash_base() + HASH_DIN, data);
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return 0;
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}
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static void hash_hw_init(enum stm32_hash_algo_mode mode)
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{
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uint32_t reg;
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reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT);
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switch (mode) {
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case HASH_MD5SUM:
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reg |= HASH_CR_ALGO_MD5;
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stm32_hash.digest_size = MD5_DIGEST_SIZE;
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break;
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case HASH_SHA1:
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reg |= HASH_CR_ALGO_SHA1;
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stm32_hash.digest_size = SHA1_DIGEST_SIZE;
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break;
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case HASH_SHA224:
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reg |= HASH_CR_ALGO_SHA224;
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stm32_hash.digest_size = SHA224_DIGEST_SIZE;
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break;
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/* Default selected algo is SHA256 */
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case HASH_SHA256:
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default:
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reg |= HASH_CR_ALGO_SHA256;
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stm32_hash.digest_size = SHA256_DIGEST_SIZE;
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break;
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}
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mmio_write_32(hash_base() + HASH_CR, reg);
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}
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static int hash_get_digest(uint8_t *digest)
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{
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int ret;
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uint32_t i;
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uint32_t dsg;
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ret = hash_wait_computation();
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if (ret != 0) {
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return ret;
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}
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for (i = 0U; i < (stm32_hash.digest_size / sizeof(uint32_t)); i++) {
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dsg = __builtin_bswap32(mmio_read_32(hash_base() +
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HASH_HREG(i)));
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memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t));
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}
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#if defined(IMAGE_BL2)
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/*
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* Clean hardware context as HASH could be used later
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* by non-secure software
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*/
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hash_hw_init(HASH_SHA256);
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#endif
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return 0;
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}
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int stm32_hash_update(const uint8_t *buffer, size_t length)
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{
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size_t remain_length = length;
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int ret = 0;
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if ((length == 0U) || (buffer == NULL)) {
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return 0;
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}
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stm32mp_clk_enable(stm32_hash.clock);
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if (stm32_remain.length != 0U) {
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uint32_t copysize;
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copysize = MIN((sizeof(uint32_t) - stm32_remain.length),
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length);
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memcpy(((uint8_t *)&stm32_remain.buffer) + stm32_remain.length,
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buffer, copysize);
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remain_length -= copysize;
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buffer += copysize;
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if (stm32_remain.length == sizeof(uint32_t)) {
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ret = hash_write_data(stm32_remain.buffer);
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if (ret != 0) {
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goto exit;
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}
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zeromem(&stm32_remain, sizeof(stm32_remain));
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}
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}
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while (remain_length / sizeof(uint32_t) != 0U) {
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uint32_t tmp_buf;
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memcpy(&tmp_buf, buffer, sizeof(uint32_t));
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ret = hash_write_data(tmp_buf);
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if (ret != 0) {
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goto exit;
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}
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buffer += sizeof(uint32_t);
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remain_length -= sizeof(uint32_t);
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}
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if (remain_length != 0U) {
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assert(stm32_remain.length == 0U);
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memcpy((uint8_t *)&stm32_remain.buffer, buffer, remain_length);
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stm32_remain.length = remain_length;
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}
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exit:
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stm32mp_clk_disable(stm32_hash.clock);
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return ret;
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}
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int stm32_hash_final(uint8_t *digest)
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{
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int ret;
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stm32mp_clk_enable(stm32_hash.clock);
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if (stm32_remain.length != 0U) {
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ret = hash_write_data(stm32_remain.buffer);
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if (ret != 0) {
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stm32mp_clk_disable(stm32_hash.clock);
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return ret;
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}
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mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK,
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8U * stm32_remain.length);
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zeromem(&stm32_remain, sizeof(stm32_remain));
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}
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mmio_setbits_32(hash_base() + HASH_STR, HASH_STR_DCAL);
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ret = hash_get_digest(digest);
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stm32mp_clk_disable(stm32_hash.clock);
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return ret;
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}
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int stm32_hash_final_update(const uint8_t *buffer, uint32_t length,
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uint8_t *digest)
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{
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int ret;
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ret = stm32_hash_update(buffer, length);
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if (ret != 0) {
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return ret;
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}
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return stm32_hash_final(digest);
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}
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void stm32_hash_init(enum stm32_hash_algo_mode mode)
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{
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stm32mp_clk_enable(stm32_hash.clock);
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hash_hw_init(mode);
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stm32mp_clk_disable(stm32_hash.clock);
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zeromem(&stm32_remain, sizeof(stm32_remain));
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}
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int stm32_hash_register(void)
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{
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struct dt_node_info hash_info;
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int node;
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for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT);
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node != -FDT_ERR_NOTFOUND;
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node = dt_get_node(&hash_info, node, DT_HASH_COMPAT)) {
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#if defined(IMAGE_BL2)
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if (hash_info.status != DT_DISABLED) {
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break;
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}
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#else
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if (hash_info.status == DT_SECURE) {
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break;
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}
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#endif
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}
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if (node == -FDT_ERR_NOTFOUND) {
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return -ENODEV;
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}
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if (hash_info.clock < 0) {
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return -EINVAL;
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}
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stm32_hash.base = hash_info.base;
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stm32_hash.clock = hash_info.clock;
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stm32mp_clk_enable(stm32_hash.clock);
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if (hash_info.reset >= 0) {
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stm32mp_reset_assert((unsigned long)hash_info.reset);
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udelay(20);
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stm32mp_reset_deassert((unsigned long)hash_info.reset);
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}
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stm32mp_clk_disable(stm32_hash.clock);
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return 0;
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}
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_HASH_H
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#define STM32_HASH_H
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enum stm32_hash_algo_mode {
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HASH_MD5SUM,
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HASH_SHA1,
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HASH_SHA224,
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HASH_SHA256
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};
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int stm32_hash_update(const uint8_t *buffer, uint32_t length);
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int stm32_hash_final(uint8_t *digest);
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int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
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uint8_t *digest);
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void stm32_hash_init(enum stm32_hash_algo_mode mode);
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int stm32_hash_register(void);
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#endif /* STM32_HASH_H */
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