nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These other boards are not verified yet. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
This commit is contained in:
Pankaj Gupta
parent
c6d9fdbc78
commit
b35ce0c413
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#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#-----------------------------------------------------------------------------
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# MMDC ddr cntlr driver files
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DDR_DRIVERS_PATH := drivers/nxp/ddr
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DDR_CNTLR_SOURCES := ${DDR_DRIVERS_PATH}/fsl-mmdc/fsl_mmdc.c \
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${DDR_DRIVERS_PATH}/nxp-ddr/utility.c \
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${DDR_DRIVERS_PATH}/nxp-ddr/ddr.c \
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${DDR_DRIVERS_PATH}/nxp-ddr/ddrc.c
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PLAT_INCLUDES += -I$(DDR_DRIVERS_PATH)/include \
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-I$(DDR_DRIVERS_PATH)/fsl-mmdc
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#------------------------------------------------
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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/*
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* Generic driver for Freescale MMDC(Multi Mode DDR Controller).
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*/
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#include <errno.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <common/debug.h>
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#include "ddr_io.h"
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#include <drivers/delay_timer.h>
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#include <fsl_mmdc.h>
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static void set_wait_for_bits_clear(void *ptr, unsigned int value,
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unsigned int bits)
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{
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int timeout = 1000;
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ddr_out32(ptr, value);
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while ((ddr_in32(ptr) & bits) != 0) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0) {
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INFO("Error: %llx", (unsigned long long)ptr);
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INFO(" wait for clear timeout.\n");
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}
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}
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void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr)
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{
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struct mmdc_regs *mmdc = (struct mmdc_regs *)nxp_ddr_addr;
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unsigned int tmp;
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/* 1. set configuration request */
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ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
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/* 2. configure the desired timing parameters */
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ddr_out32(&mmdc->mdotc, priv->mdotc);
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ddr_out32(&mmdc->mdcfg0, priv->mdcfg0);
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ddr_out32(&mmdc->mdcfg1, priv->mdcfg1);
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ddr_out32(&mmdc->mdcfg2, priv->mdcfg2);
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/* 3. configure DDR type and other miscellaneous parameters */
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ddr_out32(&mmdc->mdmisc, priv->mdmisc);
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ddr_out32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
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ddr_out32(&mmdc->mdrwd, priv->mdrwd);
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ddr_out32(&mmdc->mpodtctrl, priv->mpodtctrl);
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/* 4. configure the required delay while leaving reset */
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ddr_out32(&mmdc->mdor, priv->mdor);
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/* 5. configure DDR physical parameters */
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/* set row/column address width, burst length, data bus width */
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tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
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ddr_out32(&mmdc->mdctl, tmp);
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/* configure address space partition */
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ddr_out32(&mmdc->mdasp, priv->mdasp);
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/* 6. perform a ZQ calibration - not needed here, doing in #8b */
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/* 7. enable MMDC with the desired chip select */
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#if (DDRC_NUM_CS == 1)
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ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0);
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#elif (DDRC_NUM_CS == 2)
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ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
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#else
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#error "Unsupported DDRC_NUM_CS"
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#endif
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/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_2);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_1);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
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CMD_ADDR_LSB_MR_ADDR(0x30) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
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/* 8b. ZQ calibration */
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ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) |
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MDSCR_ENABLE_CON_REQ |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
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MPZQHWCTRL_ZQ_HW_FORCE);
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/* 9a. calibrations now, wr lvl */
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) | MDSCR_WL_EN |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
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set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
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MPWLGCR_HW_WL_EN);
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mdelay(1);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
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ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
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mdelay(1);
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/* 9b. read DQS gating calibration */
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ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
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ddr_out32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
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/* set absolute read delay offset */
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if (priv->mprddlctl != 0) {
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ddr_out32(&mmdc->mprddlctl, priv->mprddlctl);
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} else {
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ddr_out32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
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}
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set_wait_for_bits_clear(&mmdc->mpdgctrl0,
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AUTO_RD_DQS_GATING_CALIBRATION_EN,
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AUTO_RD_DQS_GATING_CALIBRATION_EN);
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ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3);
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/* 9c. read calibration */
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ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
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ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
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ddr_out32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
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set_wait_for_bits_clear(&mmdc->mprddlhwctl,
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
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ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3);
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/* 10. configure power-down, self-refresh entry, exit parameters */
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ddr_out32(&mmdc->mdpdc, priv->mdpdc);
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ddr_out32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
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/* 11. ZQ config again? do nothing here */
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/* 12. refresh scheme */
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set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
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MDREF_START_REFRESH);
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/* 13. disable CON_REQ */
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ddr_out32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
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}
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef FSL_MMDC_H
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#define FSL_MMDC_H
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/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
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#define MPWLGCR_HW_WL_EN (1 << 0)
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/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
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#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
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/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
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#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
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/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
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#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
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/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
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#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
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/* MMDC Core Refresh Control Register (MMDC_MDREF) */
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#define MDREF_START_REFRESH (1 << 0)
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/* MMDC Core Special Command Register (MDSCR) */
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#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
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#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
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#define MDSCR_DISABLE_CFG_REQ (0 << 15)
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#define MDSCR_ENABLE_CON_REQ (1 << 15)
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#define MDSCR_CON_ACK (1 << 14)
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#define MDSCR_WL_EN (1 << 9)
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#define CMD_NORMAL (0 << 4)
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#define CMD_PRECHARGE (1 << 4)
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#define CMD_AUTO_REFRESH (2 << 4)
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#define CMD_LOAD_MODE_REG (3 << 4)
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#define CMD_ZQ_CALIBRATION (4 << 4)
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#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
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#define CMD_MRR (6 << 4)
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#define CMD_BANK_ADDR_0 0x0
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#define CMD_BANK_ADDR_1 0x1
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#define CMD_BANK_ADDR_2 0x2
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#define CMD_BANK_ADDR_3 0x3
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#define CMD_BANK_ADDR_4 0x4
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#define CMD_BANK_ADDR_5 0x5
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#define CMD_BANK_ADDR_6 0x6
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#define CMD_BANK_ADDR_7 0x7
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/* MMDC Core Control Register (MDCTL) */
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#define MDCTL_SDE0 (U(1) << 31)
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#define MDCTL_SDE1 (1 << 30)
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/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
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#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
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/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
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#define MMDC_MPMUR0_FRC_MSR (1 << 11)
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/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
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/* default 64 for a quarter cycle delay */
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#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
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/* MMDC Registers */
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struct mmdc_regs {
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unsigned int mdctl;
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unsigned int mdpdc;
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unsigned int mdotc;
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unsigned int mdcfg0;
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unsigned int mdcfg1;
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unsigned int mdcfg2;
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unsigned int mdmisc;
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unsigned int mdscr;
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unsigned int mdref;
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unsigned int res1[2];
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unsigned int mdrwd;
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unsigned int mdor;
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unsigned int mdmrr;
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unsigned int mdcfg3lp;
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unsigned int mdmr4;
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unsigned int mdasp;
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unsigned int res2[239];
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unsigned int maarcr;
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unsigned int mapsr;
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unsigned int maexidr0;
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unsigned int maexidr1;
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unsigned int madpcr0;
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unsigned int madpcr1;
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unsigned int madpsr0;
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unsigned int madpsr1;
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unsigned int madpsr2;
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unsigned int madpsr3;
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unsigned int madpsr4;
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unsigned int madpsr5;
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unsigned int masbs0;
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unsigned int masbs1;
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unsigned int res3[2];
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unsigned int magenp;
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unsigned int res4[239];
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unsigned int mpzqhwctrl;
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unsigned int mpzqswctrl;
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unsigned int mpwlgcr;
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unsigned int mpwldectrl0;
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unsigned int mpwldectrl1;
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unsigned int mpwldlst;
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unsigned int mpodtctrl;
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unsigned int mprddqby0dl;
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unsigned int mprddqby1dl;
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unsigned int mprddqby2dl;
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unsigned int mprddqby3dl;
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unsigned int mpwrdqby0dl;
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unsigned int mpwrdqby1dl;
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unsigned int mpwrdqby2dl;
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unsigned int mpwrdqby3dl;
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unsigned int mpdgctrl0;
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unsigned int mpdgctrl1;
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unsigned int mpdgdlst0;
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unsigned int mprddlctl;
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unsigned int mprddlst;
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unsigned int mpwrdlctl;
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unsigned int mpwrdlst;
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unsigned int mpsdctrl;
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unsigned int mpzqlp2ctl;
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unsigned int mprddlhwctl;
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unsigned int mpwrdlhwctl;
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unsigned int mprddlhwst0;
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unsigned int mprddlhwst1;
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unsigned int mpwrdlhwst0;
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unsigned int mpwrdlhwst1;
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unsigned int mpwlhwerr;
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unsigned int mpdghwst0;
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unsigned int mpdghwst1;
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unsigned int mpdghwst2;
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unsigned int mpdghwst3;
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unsigned int mppdcmpr1;
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unsigned int mppdcmpr2;
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unsigned int mpswdar0;
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unsigned int mpswdrdr0;
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unsigned int mpswdrdr1;
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unsigned int mpswdrdr2;
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unsigned int mpswdrdr3;
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unsigned int mpswdrdr4;
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unsigned int mpswdrdr5;
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unsigned int mpswdrdr6;
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unsigned int mpswdrdr7;
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unsigned int mpmur0;
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unsigned int mpwrcadl;
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unsigned int mpdccr;
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};
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struct fsl_mmdc_info {
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unsigned int mdctl;
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unsigned int mdpdc;
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unsigned int mdotc;
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unsigned int mdcfg0;
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unsigned int mdcfg1;
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unsigned int mdcfg2;
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unsigned int mdmisc;
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unsigned int mdref;
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unsigned int mdrwd;
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unsigned int mdor;
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unsigned int mdasp;
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unsigned int mpodtctrl;
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unsigned int mpzqhwctrl;
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unsigned int mprddlctl;
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};
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void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr);
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#endif /* FSL_MMDC_H */
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@ -0,0 +1,151 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DDR_H
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#define DDR_H
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#include "ddr_io.h"
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#include "dimm.h"
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#include "immap.h"
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#ifndef DDRC_NUM_CS
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#define DDRC_NUM_CS 4
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#endif
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/*
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* This is irrespective of what is the number of DDR controller,
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* number of DIMM used. This is set to maximum
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* Max controllers = 2
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* Max num of DIMM per controlle = 2
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* MAX NUM CS = 4
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* Not to be changed.
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*/
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#define MAX_DDRC_NUM 2
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#define MAX_DIMM_NUM 2
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#define MAX_CS_NUM 4
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#include "opts.h"
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#include "regs.h"
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#include "utility.h"
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#ifdef DDR_DEBUG
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#define debug(...) INFO(__VA_ARGS__)
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#else
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#define debug(...) VERBOSE(__VA_ARGS__)
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#endif
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#ifndef DDRC_NUM_DIMM
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#define DDRC_NUM_DIMM 1
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#endif
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#define CONFIG_CS_PER_SLOT \
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(DDRC_NUM_CS / DDRC_NUM_DIMM)
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/* Record of register values computed */
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struct ddr_cfg_regs {
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struct {
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unsigned int bnds;
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unsigned int config;
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unsigned int config_2;
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} cs[MAX_CS_NUM];
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unsigned int dec[10];
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unsigned int timing_cfg[10];
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unsigned int sdram_cfg[3];
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unsigned int sdram_mode[16];
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unsigned int md_cntl;
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unsigned int interval;
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unsigned int data_init;
|
||||
unsigned int clk_cntl;
|
||||
unsigned int init_addr;
|
||||
unsigned int init_ext_addr;
|
||||
unsigned int zq_cntl;
|
||||
unsigned int wrlvl_cntl[3];
|
||||
unsigned int ddr_sr_cntr;
|
||||
unsigned int sdram_rcw[6];
|
||||
unsigned int dq_map[4];
|
||||
unsigned int eor;
|
||||
unsigned int cdr[2];
|
||||
unsigned int err_disable;
|
||||
unsigned int err_int_en;
|
||||
unsigned int tx_cfg[4];
|
||||
unsigned int debug[64];
|
||||
};
|
||||
|
||||
struct ddr_conf {
|
||||
int dimm_in_use[MAX_DIMM_NUM];
|
||||
int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
|
||||
int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
|
||||
unsigned long long cs_base_addr[MAX_CS_NUM];
|
||||
unsigned long long cs_size[MAX_CS_NUM];
|
||||
unsigned long long base_addr;
|
||||
unsigned long long total_mem;
|
||||
};
|
||||
|
||||
struct ddr_info {
|
||||
unsigned long clk;
|
||||
unsigned long long mem_base;
|
||||
unsigned int num_ctlrs;
|
||||
unsigned int dimm_on_ctlr;
|
||||
struct dimm_params dimm;
|
||||
struct memctl_opt opt;
|
||||
struct ddr_conf conf;
|
||||
struct ddr_cfg_regs ddr_reg;
|
||||
struct ccsr_ddr *ddr[MAX_DDRC_NUM];
|
||||
uint16_t *phy[MAX_DDRC_NUM];
|
||||
int *spd_addr;
|
||||
unsigned int ip_rev;
|
||||
uintptr_t phy_gen2_fw_img_buf;
|
||||
void *img_loadr;
|
||||
int warm_boot_flag;
|
||||
};
|
||||
|
||||
struct rc_timing {
|
||||
unsigned int speed_bin;
|
||||
unsigned int clk_adj;
|
||||
unsigned int wrlvl;
|
||||
};
|
||||
|
||||
struct board_timing {
|
||||
unsigned int rc;
|
||||
struct rc_timing const *p;
|
||||
unsigned int add1;
|
||||
unsigned int add2;
|
||||
};
|
||||
|
||||
enum warm_boot {
|
||||
DDR_COLD_BOOT = 0,
|
||||
DDR_WARM_BOOT = 1,
|
||||
DDR_WRM_BOOT_NT_SUPPORTED = -1,
|
||||
};
|
||||
|
||||
int disable_unused_ddrc(struct ddr_info *priv, int mask,
|
||||
uintptr_t nxp_ccn_hn_f0_addr);
|
||||
int ddr_board_options(struct ddr_info *priv);
|
||||
int compute_ddrc(const unsigned long clk,
|
||||
const struct memctl_opt *popts,
|
||||
const struct ddr_conf *conf,
|
||||
struct ddr_cfg_regs *ddr,
|
||||
const struct dimm_params *dimm_params,
|
||||
const unsigned int ip_rev);
|
||||
int compute_ddr_phy(struct ddr_info *priv);
|
||||
int ddrc_set_regs(const unsigned long clk,
|
||||
const struct ddr_cfg_regs *regs,
|
||||
const struct ccsr_ddr *ddr,
|
||||
int twopass);
|
||||
int cal_board_params(struct ddr_info *priv,
|
||||
const struct board_timing *dimm,
|
||||
int len);
|
||||
/* return bit mask of used DIMM(s) */
|
||||
int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
|
||||
long long dram_init(struct ddr_info *priv
|
||||
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
|
||||
, uintptr_t nxp_ccn_hn_f0_addr
|
||||
#endif
|
||||
);
|
||||
long long board_static_ddr(struct ddr_info *info);
|
||||
|
||||
#endif /* DDR_H */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DDR_IO_H
|
||||
#define DDR_IO_H
|
||||
|
||||
#include <endian.h>
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#define min(a, b) (((a) > (b)) ? (b) : (a))
|
||||
|
||||
#define max(a, b) (((a) > (b)) ? (a) : (b))
|
||||
|
||||
/* macro for memory barrier */
|
||||
#define mb() asm volatile("dsb sy" : : : "memory")
|
||||
|
||||
#ifdef NXP_DDR_BE
|
||||
#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
|
||||
#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\
|
||||
bswap32(v))
|
||||
#elif defined(NXP_DDR_LE)
|
||||
#define ddr_in32(a) mmio_read_32((uintptr_t)(a))
|
||||
#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v)
|
||||
#else
|
||||
#error Please define CCSR DDR register endianness
|
||||
#endif
|
||||
|
||||
#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v))
|
||||
#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v))
|
||||
#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \
|
||||
| (s))
|
||||
|
||||
#endif /* DDR_IO_H */
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DIMM_H
|
||||
#define DIMM_H
|
||||
|
||||
#define SPD_MEMTYPE_DDR4 0x0C
|
||||
|
||||
#define DDR4_SPD_MODULETYPE_MASK 0x0f
|
||||
#define DDR4_SPD_MODULETYPE_EXT 0x00
|
||||
#define DDR4_SPD_RDIMM 0x01
|
||||
#define DDR4_SPD_UDIMM 0x02
|
||||
#define DDR4_SPD_SO_DIMM 0x03
|
||||
#define DDR4_SPD_LRDIMM 0x04
|
||||
#define DDR4_SPD_MINI_RDIMM 0x05
|
||||
#define DDR4_SPD_MINI_UDIMM 0x06
|
||||
#define DDR4_SPD_72B_SO_RDIMM 0x08
|
||||
#define DDR4_SPD_72B_SO_UDIMM 0x09
|
||||
#define DDR4_SPD_16B_SO_DIMM 0x0c
|
||||
#define DDR4_SPD_32B_SO_DIMM 0x0d
|
||||
|
||||
#define SPD_SPA0_ADDRESS 0x36
|
||||
#define SPD_SPA1_ADDRESS 0x37
|
||||
|
||||
#define spd_to_ps(mtb, ftb) \
|
||||
((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10)
|
||||
|
||||
#ifdef DDR_DEBUG
|
||||
#define dump_spd(spd, len) { \
|
||||
register int i; \
|
||||
register unsigned char *buf = (void *)(spd); \
|
||||
\
|
||||
for (i = 0; i < (len); i++) { \
|
||||
print_uint(i); \
|
||||
puts("\t: 0x"); \
|
||||
print_hex(buf[i]); \
|
||||
puts("\n"); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define dump_spd(spd, len) {}
|
||||
#endif
|
||||
|
||||
/* From JEEC Standard No. 21-C release 23A */
|
||||
struct ddr4_spd {
|
||||
/* General Section: Bytes 0-127 */
|
||||
unsigned char info_size_crc; /* 0 # bytes */
|
||||
unsigned char spd_rev; /* 1 Total # bytes of SPD */
|
||||
unsigned char mem_type; /* 2 Key Byte / mem type */
|
||||
unsigned char module_type; /* 3 Key Byte / Module Type */
|
||||
unsigned char density_banks; /* 4 Density and Banks */
|
||||
unsigned char addressing; /* 5 Addressing */
|
||||
unsigned char package_type; /* 6 Package type */
|
||||
unsigned char opt_feature; /* 7 Optional features */
|
||||
unsigned char thermal_ref; /* 8 Thermal and refresh */
|
||||
unsigned char oth_opt_features; /* 9 Other optional features */
|
||||
unsigned char res_10; /* 10 Reserved */
|
||||
unsigned char module_vdd; /* 11 Module nominal voltage */
|
||||
unsigned char organization; /* 12 Module Organization */
|
||||
unsigned char bus_width; /* 13 Module Memory Bus Width */
|
||||
unsigned char therm_sensor; /* 14 Module Thermal Sensor */
|
||||
unsigned char ext_type; /* 15 Extended module type */
|
||||
unsigned char res_16;
|
||||
unsigned char timebases; /* 17 MTb and FTB */
|
||||
unsigned char tck_min; /* 18 tCKAVGmin */
|
||||
unsigned char tck_max; /* 19 TCKAVGmax */
|
||||
unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
|
||||
unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
|
||||
unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
|
||||
unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
|
||||
unsigned char taa_min; /* 24 Min CAS Latency Time */
|
||||
unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
|
||||
unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
|
||||
unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
|
||||
unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
|
||||
unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
|
||||
unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
|
||||
unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
|
||||
unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
|
||||
unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
|
||||
unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
|
||||
unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
|
||||
unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
|
||||
unsigned char tfaw_min; /* 37 tFAW, lsb */
|
||||
unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
|
||||
unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
|
||||
unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
|
||||
unsigned char res_41[60-41]; /* 41 Rserved */
|
||||
unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
|
||||
unsigned char res_78[117-78]; /* 78~116, Reserved */
|
||||
signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
|
||||
signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
|
||||
signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
|
||||
signed char fine_trc_min; /* 120 Fine offset for tRCmin */
|
||||
signed char fine_trp_min; /* 121 Fine offset for tRPmin */
|
||||
signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
|
||||
signed char fine_taa_min; /* 123 Fine offset for tAAmin */
|
||||
signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
|
||||
signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
|
||||
/* CRC: Bytes 126-127 */
|
||||
unsigned char crc[2]; /* 126-127 SPD CRC */
|
||||
|
||||
/* Module-Specific Section: Bytes 128-255 */
|
||||
union {
|
||||
struct {
|
||||
/* 128 (Unbuffered) Module Nominal Height */
|
||||
unsigned char mod_height;
|
||||
/* 129 (Unbuffered) Module Maximum Thickness */
|
||||
unsigned char mod_thickness;
|
||||
/* 130 (Unbuffered) Reference Raw Card Used */
|
||||
unsigned char ref_raw_card;
|
||||
/* 131 (Unbuffered) Address Mapping from
|
||||
* Edge Connector to DRAM
|
||||
*/
|
||||
unsigned char addr_mapping;
|
||||
/* 132~253 (Unbuffered) Reserved */
|
||||
unsigned char res_132[254-132];
|
||||
/* 254~255 CRC */
|
||||
unsigned char crc[2];
|
||||
} unbuffered;
|
||||
struct {
|
||||
/* 128 (Registered) Module Nominal Height */
|
||||
unsigned char mod_height;
|
||||
/* 129 (Registered) Module Maximum Thickness */
|
||||
unsigned char mod_thickness;
|
||||
/* 130 (Registered) Reference Raw Card Used */
|
||||
unsigned char ref_raw_card;
|
||||
/* 131 DIMM Module Attributes */
|
||||
unsigned char modu_attr;
|
||||
/* 132 RDIMM Thermal Heat Spreader Solution */
|
||||
unsigned char thermal;
|
||||
/* 133 Register Manufacturer ID Code, LSB */
|
||||
unsigned char reg_id_lo;
|
||||
/* 134 Register Manufacturer ID Code, MSB */
|
||||
unsigned char reg_id_hi;
|
||||
/* 135 Register Revision Number */
|
||||
unsigned char reg_rev;
|
||||
/* 136 Address mapping from register to DRAM */
|
||||
unsigned char reg_map;
|
||||
unsigned char ca_stren;
|
||||
unsigned char clk_stren;
|
||||
/* 139~253 Reserved */
|
||||
unsigned char res_139[254-139];
|
||||
/* 254~255 CRC */
|
||||
unsigned char crc[2];
|
||||
} registered;
|
||||
struct {
|
||||
/* 128 (Loadreduced) Module Nominal Height */
|
||||
unsigned char mod_height;
|
||||
/* 129 (Loadreduced) Module Maximum Thickness */
|
||||
unsigned char mod_thickness;
|
||||
/* 130 (Loadreduced) Reference Raw Card Used */
|
||||
unsigned char ref_raw_card;
|
||||
/* 131 DIMM Module Attributes */
|
||||
unsigned char modu_attr;
|
||||
/* 132 RDIMM Thermal Heat Spreader Solution */
|
||||
unsigned char thermal;
|
||||
/* 133 Register Manufacturer ID Code, LSB */
|
||||
unsigned char reg_id_lo;
|
||||
/* 134 Register Manufacturer ID Code, MSB */
|
||||
unsigned char reg_id_hi;
|
||||
/* 135 Register Revision Number */
|
||||
unsigned char reg_rev;
|
||||
/* 136 Address mapping from register to DRAM */
|
||||
unsigned char reg_map;
|
||||
/* 137 Register Output Drive Strength for CMD/Add*/
|
||||
unsigned char reg_drv;
|
||||
/* 138 Register Output Drive Strength for CK */
|
||||
unsigned char reg_drv_ck;
|
||||
/* 139 Data Buffer Revision Number */
|
||||
unsigned char data_buf_rev;
|
||||
/* 140 DRAM VrefDQ for Package Rank 0 */
|
||||
unsigned char vrefqe_r0;
|
||||
/* 141 DRAM VrefDQ for Package Rank 1 */
|
||||
unsigned char vrefqe_r1;
|
||||
/* 142 DRAM VrefDQ for Package Rank 2 */
|
||||
unsigned char vrefqe_r2;
|
||||
/* 143 DRAM VrefDQ for Package Rank 3 */
|
||||
unsigned char vrefqe_r3;
|
||||
/* 144 Data Buffer VrefDQ for DRAM Interface */
|
||||
unsigned char data_intf;
|
||||
/*
|
||||
* 145 Data Buffer MDQ Drive Strength and RTT
|
||||
* for data rate <= 1866
|
||||
*/
|
||||
unsigned char data_drv_1866;
|
||||
/*
|
||||
* 146 Data Buffer MDQ Drive Strength and RTT
|
||||
* for 1866 < data rate <= 2400
|
||||
*/
|
||||
unsigned char data_drv_2400;
|
||||
/*
|
||||
* 147 Data Buffer MDQ Drive Strength and RTT
|
||||
* for 2400 < data rate <= 3200
|
||||
*/
|
||||
unsigned char data_drv_3200;
|
||||
/* 148 DRAM Drive Strength */
|
||||
unsigned char dram_drv;
|
||||
/*
|
||||
* 149 DRAM ODT (RTT_WR, RTT_NOM)
|
||||
* for data rate <= 1866
|
||||
*/
|
||||
unsigned char dram_odt_1866;
|
||||
/*
|
||||
* 150 DRAM ODT (RTT_WR, RTT_NOM)
|
||||
* for 1866 < data rate <= 2400
|
||||
*/
|
||||
unsigned char dram_odt_2400;
|
||||
/*
|
||||
* 151 DRAM ODT (RTT_WR, RTT_NOM)
|
||||
* for 2400 < data rate <= 3200
|
||||
*/
|
||||
unsigned char dram_odt_3200;
|
||||
/*
|
||||
* 152 DRAM ODT (RTT_PARK)
|
||||
* for data rate <= 1866
|
||||
*/
|
||||
unsigned char dram_odt_park_1866;
|
||||
/*
|
||||
* 153 DRAM ODT (RTT_PARK)
|
||||
* for 1866 < data rate <= 2400
|
||||
*/
|
||||
unsigned char dram_odt_park_2400;
|
||||
/*
|
||||
* 154 DRAM ODT (RTT_PARK)
|
||||
* for 2400 < data rate <= 3200
|
||||
*/
|
||||
unsigned char dram_odt_park_3200;
|
||||
unsigned char res_155[254-155]; /* Reserved */
|
||||
/* 254~255 CRC */
|
||||
unsigned char crc[2];
|
||||
} loadreduced;
|
||||
unsigned char uc[128]; /* 128-255 Module-Specific Section */
|
||||
} mod_section;
|
||||
|
||||
unsigned char res_256[320-256]; /* 256~319 Reserved */
|
||||
|
||||
/* Module supplier's data: Byte 320~383 */
|
||||
unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
|
||||
unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
|
||||
unsigned char mloc; /* 322 Mfg Location */
|
||||
unsigned char mdate[2]; /* 323~324 Mfg Date */
|
||||
unsigned char sernum[4]; /* 325~328 Module Serial Number */
|
||||
unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
|
||||
unsigned char mrev; /* 349 Module Revision Code */
|
||||
unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
|
||||
unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
|
||||
unsigned char stepping; /* 352 DRAM stepping */
|
||||
unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
|
||||
unsigned char res_382[2]; /* 382~383 Reserved */
|
||||
};
|
||||
|
||||
/* Parameters for a DDR dimm computed from the SPD */
|
||||
struct dimm_params {
|
||||
/* DIMM organization parameters */
|
||||
char mpart[19]; /* guaranteed null terminated */
|
||||
|
||||
unsigned int n_ranks;
|
||||
unsigned int die_density;
|
||||
unsigned long long rank_density;
|
||||
unsigned long long capacity;
|
||||
unsigned int primary_sdram_width;
|
||||
unsigned int ec_sdram_width;
|
||||
unsigned int rdimm;
|
||||
unsigned int package_3ds; /* number of dies in 3DS */
|
||||
unsigned int device_width; /* x4, x8, x16 components */
|
||||
unsigned int rc;
|
||||
|
||||
/* SDRAM device parameters */
|
||||
unsigned int n_row_addr;
|
||||
unsigned int n_col_addr;
|
||||
unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
|
||||
unsigned int bank_addr_bits;
|
||||
unsigned int bank_group_bits;
|
||||
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
|
||||
|
||||
/* mirrored DIMMs */
|
||||
unsigned int mirrored_dimm; /* only for ddr3 */
|
||||
|
||||
/* DIMM timing parameters */
|
||||
|
||||
int mtb_ps; /* medium timebase ps */
|
||||
int ftb_10th_ps; /* fine timebase, in 1/10 ps */
|
||||
int taa_ps; /* minimum CAS latency time */
|
||||
int tfaw_ps; /* four active window delay */
|
||||
|
||||
/*
|
||||
* SDRAM clock periods
|
||||
* The range for these are 1000-10000 so a short should be sufficient
|
||||
*/
|
||||
int tckmin_x_ps;
|
||||
int tckmax_ps;
|
||||
|
||||
/* SPD-defined CAS latencies */
|
||||
unsigned int caslat_x;
|
||||
|
||||
/* basic timing parameters */
|
||||
int trcd_ps;
|
||||
int trp_ps;
|
||||
int tras_ps;
|
||||
|
||||
int trfc1_ps;
|
||||
int trfc2_ps;
|
||||
int trfc4_ps;
|
||||
int trrds_ps;
|
||||
int trrdl_ps;
|
||||
int tccdl_ps;
|
||||
int trfc_slr_ps;
|
||||
|
||||
int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
|
||||
int twr_ps; /* 15ns for all speed bins */
|
||||
|
||||
unsigned int refresh_rate_ps;
|
||||
unsigned int extended_op_srt;
|
||||
|
||||
/* RDIMM */
|
||||
unsigned char rcw[16]; /* Register Control Word 0-15 */
|
||||
unsigned int dq_mapping[18];
|
||||
unsigned int dq_mapping_ors;
|
||||
};
|
||||
|
||||
int read_spd(unsigned char chip, void *buf, int len);
|
||||
int crc16(unsigned char *ptr, int count);
|
||||
int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm);
|
||||
|
||||
#endif /* DIMM_H */
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DDR_IMMAP_H
|
||||
#define DDR_IMMAP_H
|
||||
|
||||
#define DDR_DBUS_64 0
|
||||
#define DDR_DBUS_32 1
|
||||
#define DDR_DBUS_16 2
|
||||
|
||||
/*
|
||||
* DDRC register file for DDRC 5.0 and above
|
||||
*/
|
||||
struct ccsr_ddr {
|
||||
struct {
|
||||
unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */
|
||||
unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */
|
||||
} bnds[4];
|
||||
unsigned char res_20[0x40 - 0x20];
|
||||
unsigned int dec[10]; /* 0x40 */
|
||||
unsigned char res_68[0x80 - 0x68];
|
||||
unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */
|
||||
unsigned char res_90[48];
|
||||
unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */
|
||||
unsigned char res_d0[48];
|
||||
unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
|
||||
unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
|
||||
unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
|
||||
unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
|
||||
unsigned int sdram_cfg; /* SDRAM Control Configuration */
|
||||
unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
|
||||
unsigned int sdram_mode; /* SDRAM Mode Configuration */
|
||||
unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
|
||||
unsigned int sdram_md_cntl; /* SDRAM Mode Control */
|
||||
unsigned int sdram_interval; /* SDRAM Interval Configuration */
|
||||
unsigned int sdram_data_init; /* SDRAM Data initialization */
|
||||
unsigned char res_12c[4];
|
||||
unsigned int sdram_clk_cntl; /* SDRAM Clock Control */
|
||||
unsigned char res_134[20];
|
||||
unsigned int init_addr; /* training init addr */
|
||||
unsigned int init_ext_addr; /* training init extended addr */
|
||||
unsigned char res_150[16];
|
||||
unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
|
||||
unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */
|
||||
unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */
|
||||
unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */
|
||||
unsigned int zq_cntl; /* ZQ calibration control*/
|
||||
unsigned int wrlvl_cntl; /* write leveling control*/
|
||||
unsigned char reg_178[4];
|
||||
unsigned int ddr_sr_cntr; /* self refresh counter */
|
||||
unsigned int ddr_sdram_rcw_1; /* Control Words 1 */
|
||||
unsigned int ddr_sdram_rcw_2; /* Control Words 2 */
|
||||
unsigned char reg_188[8];
|
||||
unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */
|
||||
unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */
|
||||
unsigned char res_198[0x1a0-0x198];
|
||||
unsigned int ddr_sdram_rcw_3;
|
||||
unsigned int ddr_sdram_rcw_4;
|
||||
unsigned int ddr_sdram_rcw_5;
|
||||
unsigned int ddr_sdram_rcw_6;
|
||||
unsigned char res_1b0[0x200-0x1b0];
|
||||
unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */
|
||||
unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */
|
||||
unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */
|
||||
unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */
|
||||
unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */
|
||||
unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */
|
||||
unsigned char res_218[0x220-0x218];
|
||||
unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */
|
||||
unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */
|
||||
unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */
|
||||
unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */
|
||||
unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */
|
||||
unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */
|
||||
unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */
|
||||
unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */
|
||||
unsigned char res_240[0x250-0x240];
|
||||
unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */
|
||||
unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */
|
||||
unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */
|
||||
unsigned char res_258[0x260-0x25c];
|
||||
unsigned int sdram_cfg_3;
|
||||
unsigned char res_264[0x270-0x264];
|
||||
unsigned int sdram_md_cntl_2;
|
||||
unsigned char res_274[0x400-0x274];
|
||||
unsigned int dq_map[4];
|
||||
unsigned char res_410[0x800-0x410];
|
||||
unsigned int tx_cfg[4];
|
||||
unsigned char res_810[0xb20-0x810];
|
||||
unsigned int ddr_dsr1; /* Debug Status 1 */
|
||||
unsigned int ddr_dsr2; /* Debug Status 2 */
|
||||
unsigned int ddr_cdr1; /* Control Driver 1 */
|
||||
unsigned int ddr_cdr2; /* Control Driver 2 */
|
||||
unsigned char res_b30[200];
|
||||
unsigned int ip_rev1; /* IP Block Revision 1 */
|
||||
unsigned int ip_rev2; /* IP Block Revision 2 */
|
||||
unsigned int eor; /* Enhanced Optimization Register */
|
||||
unsigned char res_c04[252];
|
||||
unsigned int mtcr; /* Memory Test Control Register */
|
||||
unsigned char res_d04[28];
|
||||
unsigned int mtp[10]; /* Memory Test Patterns */
|
||||
unsigned char res_d48[184];
|
||||
unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/
|
||||
unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/
|
||||
unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */
|
||||
unsigned char res_e0c[20];
|
||||
unsigned int capture_data_hi; /* Data Path Read Capture High */
|
||||
unsigned int capture_data_lo; /* Data Path Read Capture Low */
|
||||
unsigned int capture_ecc; /* Data Path Read Capture ECC */
|
||||
unsigned char res_e2c[20];
|
||||
unsigned int err_detect; /* Error Detect */
|
||||
unsigned int err_disable; /* Error Disable */
|
||||
unsigned int err_int_en;
|
||||
unsigned int capture_attributes; /* Error Attrs Capture */
|
||||
unsigned int capture_address; /* Error Addr Capture */
|
||||
unsigned int capture_ext_address; /* Error Extended Addr Capture */
|
||||
unsigned int err_sbe; /* Single-Bit ECC Error Management */
|
||||
unsigned char res_e5c[164];
|
||||
unsigned int debug[64]; /* debug_1 to debug_64 */
|
||||
};
|
||||
#endif /* DDR_IMMAP_H */
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DDR_OPTS_H
|
||||
#define DDR_OPTS_H
|
||||
|
||||
#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
|
||||
|
||||
#define DDR_BC4 4 /* burst chop */
|
||||
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
|
||||
#define DDR_BL8 8 /* burst length 8 */
|
||||
|
||||
#define DDR4_RTT_OFF 0
|
||||
#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
|
||||
#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
|
||||
#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
|
||||
#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
|
||||
#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
|
||||
#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
|
||||
#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
|
||||
#define DDR4_RTT_WR_OFF 0
|
||||
#define DDR4_RTT_WR_120_OHM 1
|
||||
#define DDR4_RTT_WR_240_OHM 2
|
||||
#define DDR4_RTT_WR_HZ 3
|
||||
#define DDR4_RTT_WR_80_OHM 4
|
||||
#define DDR_ODT_NEVER 0x0
|
||||
#define DDR_ODT_CS 0x1
|
||||
#define DDR_ODT_ALL_OTHER_CS 0x2
|
||||
#define DDR_ODT_OTHER_DIMM 0x3
|
||||
#define DDR_ODT_ALL 0x4
|
||||
#define DDR_ODT_SAME_DIMM 0x5
|
||||
#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
|
||||
#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
|
||||
#define DDR_BA_INTLV_CS01 0x40
|
||||
#define DDR_BA_INTLV_CS0123 0x64
|
||||
#define DDR_BA_NONE 0
|
||||
#define DDR_256B_INTLV 0x8
|
||||
|
||||
struct memctl_opt {
|
||||
int rdimm;
|
||||
unsigned int dbw_cap_shift;
|
||||
struct local_opts_s {
|
||||
unsigned int auto_precharge;
|
||||
unsigned int odt_rd_cfg;
|
||||
unsigned int odt_wr_cfg;
|
||||
unsigned int odt_rtt_norm;
|
||||
unsigned int odt_rtt_wr;
|
||||
} cs_odt[DDRC_NUM_CS];
|
||||
int ctlr_intlv;
|
||||
unsigned int ctlr_intlv_mode;
|
||||
unsigned int ba_intlv;
|
||||
int addr_hash;
|
||||
int ecc_mode;
|
||||
int ctlr_init_ecc;
|
||||
int self_refresh_in_sleep;
|
||||
int self_refresh_irq_en;
|
||||
int dynamic_power;
|
||||
/* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
|
||||
unsigned int data_bus_dimm;
|
||||
unsigned int data_bus_used; /* on individual board */
|
||||
unsigned int burst_length; /* BC4, OTF and BL8 */
|
||||
int otf_burst_chop_en;
|
||||
int mirrored_dimm;
|
||||
int quad_rank_present;
|
||||
int output_driver_impedance;
|
||||
int ap_en;
|
||||
int x4_en;
|
||||
|
||||
int caslat_override;
|
||||
unsigned int caslat_override_value;
|
||||
int addt_lat_override;
|
||||
unsigned int addt_lat_override_value;
|
||||
|
||||
unsigned int clk_adj;
|
||||
unsigned int cpo_sample;
|
||||
unsigned int wr_data_delay;
|
||||
|
||||
unsigned int cswl_override;
|
||||
unsigned int wrlvl_override;
|
||||
unsigned int wrlvl_sample;
|
||||
unsigned int wrlvl_start;
|
||||
unsigned int wrlvl_ctl_2;
|
||||
unsigned int wrlvl_ctl_3;
|
||||
|
||||
int half_strength_drive_en;
|
||||
int twot_en;
|
||||
int threet_en;
|
||||
unsigned int bstopre;
|
||||
unsigned int tfaw_ps;
|
||||
|
||||
int rtt_override;
|
||||
unsigned int rtt_override_value;
|
||||
unsigned int rtt_wr_override_value;
|
||||
unsigned int rtt_park;
|
||||
|
||||
int auto_self_refresh_en;
|
||||
unsigned int sr_it;
|
||||
unsigned int ddr_cdr1;
|
||||
unsigned int ddr_cdr2;
|
||||
|
||||
unsigned int trwt_override;
|
||||
unsigned int trwt;
|
||||
unsigned int twrt;
|
||||
unsigned int trrt;
|
||||
unsigned int twwt;
|
||||
|
||||
unsigned int vref_phy;
|
||||
unsigned int vref_dimm;
|
||||
unsigned int odt;
|
||||
unsigned int phy_tx_impedance;
|
||||
unsigned int phy_atx_impedance;
|
||||
unsigned int skip2d;
|
||||
};
|
||||
|
||||
#endif /* DDR_OPTS_H */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DDR_REG_H
|
||||
#define DDR_REG_H
|
||||
|
||||
#define SDRAM_CS_CONFIG_EN 0x80000000
|
||||
|
||||
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
|
||||
*/
|
||||
#define SDRAM_CFG_MEM_EN 0x80000000
|
||||
#define SDRAM_CFG_SREN 0x40000000
|
||||
#define SDRAM_CFG_ECC_EN 0x20000000
|
||||
#define SDRAM_CFG_RD_EN 0x10000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
|
||||
#define SDRAM_CFG_DYN_PWR 0x00200000
|
||||
#define SDRAM_CFG_DBW_MASK 0x00180000
|
||||
#define SDRAM_CFG_DBW_SHIFT 19
|
||||
#define SDRAM_CFG_32_BW 0x00080000
|
||||
#define SDRAM_CFG_16_BW 0x00100000
|
||||
#define SDRAM_CFG_8_BW 0x00180000
|
||||
#define SDRAM_CFG_8_BE 0x00040000
|
||||
#define SDRAM_CFG_2T_EN 0x00008000
|
||||
#define SDRAM_CFG_MEM_HLT 0x00000002
|
||||
#define SDRAM_CFG_BI 0x00000001
|
||||
|
||||
#define SDRAM_CFG2_FRC_SR 0x80000000
|
||||
#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR)
|
||||
#define SDRAM_CFG2_D_INIT 0x00000010
|
||||
#define SDRAM_CFG2_AP_EN 0x00000020
|
||||
#define SDRAM_CFG2_ODT_ONLY_READ 2
|
||||
|
||||
#define SDRAM_CFG3_DDRC_RST 0x80000000
|
||||
|
||||
#define SDRAM_INTERVAL_REFINT 0xFFFF0000
|
||||
#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT)
|
||||
#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
|
||||
|
||||
/* DDR_MD_CNTL */
|
||||
#define MD_CNTL_MD_EN 0x80000000
|
||||
#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
|
||||
#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
|
||||
#define MD_CNTL_CKE(x) (((x) & 0x3) << 20)
|
||||
|
||||
/* DDR_CDR1 */
|
||||
#define DDR_CDR1_DHC_EN 0x80000000
|
||||
#define DDR_CDR1_ODT_SHIFT 17
|
||||
#define DDR_CDR1_ODT_MASK 0x6
|
||||
#define DDR_CDR2_ODT_MASK 0x1
|
||||
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
|
||||
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
|
||||
#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
|
||||
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
|
||||
#define DDR_CDR2_VREF_RANGE_2 0x00000040
|
||||
#define DDR_CDR_ODT_OFF 0x0
|
||||
#define DDR_CDR_ODT_100ohm 0x1
|
||||
#define DDR_CDR_ODT_120OHM 0x2
|
||||
#define DDR_CDR_ODT_80ohm 0x3
|
||||
#define DDR_CDR_ODT_60ohm 0x4
|
||||
#define DDR_CDR_ODT_40ohm 0x5
|
||||
#define DDR_CDR_ODT_50ohm 0x6
|
||||
#define DDR_CDR_ODT_30ohm 0x7
|
||||
|
||||
|
||||
/* DDR ERR_DISABLE */
|
||||
#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
|
||||
#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */
|
||||
#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */
|
||||
|
||||
/* Mode Registers */
|
||||
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
|
||||
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
|
||||
|
||||
/* DDR DSR2 register */
|
||||
#define DDR_DSR_2_PHY_INIT_CMPLT 0x4
|
||||
|
||||
/* SDRAM TIMING_CFG_10 register */
|
||||
#define DDR_TIMING_CFG_10_T_STAB 0x7FFF
|
||||
|
||||
/* DEBUG 2 register */
|
||||
#define DDR_DBG_2_MEM_IDLE 0x00000002
|
||||
|
||||
/* DEBUG 26 register */
|
||||
#define DDR_DEBUG_26_BIT_6 (0x1 << 6)
|
||||
#define DDR_DEBUG_26_BIT_7 (0x1 << 7)
|
||||
#define DDR_DEBUG_26_BIT_12 (0x1 << 12)
|
||||
#define DDR_DEBUG_26_BIT_13 (0x1 << 13)
|
||||
#define DDR_DEBUG_26_BIT_14 (0x1 << 14)
|
||||
#define DDR_DEBUG_26_BIT_15 (0x1 << 15)
|
||||
#define DDR_DEBUG_26_BIT_16 (0x1 << 16)
|
||||
#define DDR_DEBUG_26_BIT_17 (0x1 << 17)
|
||||
#define DDR_DEBUG_26_BIT_18 (0x1 << 18)
|
||||
#define DDR_DEBUG_26_BIT_19 (0x1 << 19)
|
||||
#define DDR_DEBUG_26_BIT_24 (0x1 << 24)
|
||||
#define DDR_DEBUG_26_BIT_25 (0x1 << 25)
|
||||
|
||||
#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24)
|
||||
|
||||
/* DEBUG_29 register */
|
||||
#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
|
||||
|
||||
#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
|
||||
|
||||
#endif /* DDR_REG_H */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef UTILITY_H
|
||||
#define UTILITY_H
|
||||
|
||||
#include <dcfg.h>
|
||||
|
||||
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
|
||||
#define CCN_HN_F_SAM_CTL 0x8
|
||||
#define CCN_HN_F_REGION_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num);
|
||||
unsigned int get_memory_clk_ps(unsigned long clk);
|
||||
unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos);
|
||||
unsigned int get_ddrc_version(const struct ccsr_ddr *ddr);
|
||||
void print_ddr_info(struct ccsr_ddr *ddr);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
Table for dynamic ODT for DDR4 with PHY generation 2
|
||||
====================================================
|
||||
Two-slot system
|
||||
Only symmetric configurations are supported for interleaving. Non-symmetric
|
||||
configurations are possible but not covered here. First slot empty is possbile
|
||||
but prohibited for simplicity.
|
||||
+-----------------------+-------------+---------------+-----------------------------+-----------------------------+
|
||||
| Configuration | |DRAM controller| Slot 1 | Slot 2 |
|
||||
+-----------+-----------+-------------+-------+-------+--------------+--------------+--------------+--------------+
|
||||
| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
|
||||
| Slot 1 | Slot 2 | Write/Read | Write | Read |-------+------+-------+------+-------+------+-------+------+
|
||||
| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
|
||||
+-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | |Rank 1| off | 60 | 240 | off | 60 | 240 | 60 | 60 | 60 | 60 |
|
||||
| | |Slot 1|------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | |Rank 2| off | 60 | 60 | 240 | 240 | off | 60 | 60 | 60 | 60 |
|
||||
| Dual Rank | Dual Rank |------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | |Rank 1| off | 60 | 60 | 60 | 60 | 60 | 240 | off | 60 | 240 |
|
||||
| | |Slot 2|------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | |Rank 2| off | 60 | 60 | 60 | 60 | 60 | 60 | 240 | 240 | off |
|
||||
+-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | Slot 1 | off | 60 | 80 | off | | | | | | |
|
||||
|Single Rank|Single Rank|-------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|
||||
| | | Slot 2 | off | 60 | | | | | 80 | off |
|
||||
+-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+
|
||||
| | | |Rank 1| off | 80 | 80 | off | off | off |
|
||||
| Dual Rank | |Slot 1|------+-------+-------+-------+------+-------+------+
|
||||
| | | |Rank 2| off | 80 | 80 | off | off | off |
|
||||
+-----------+-----------+-------------+-------+-------+-------+------+-------+------+
|
||||
|Single Rank| | Slot 1 | off | 80 | 80 | off |
|
||||
+-----------+-----------+-------------+-------+-------+-------+------+
|
||||
|
|
@ -0,0 +1,930 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#ifndef CONFIG_DDR_NODIMM
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
#include <nxp_timer.h>
|
||||
|
||||
struct dynamic_odt {
|
||||
unsigned int odt_rd_cfg;
|
||||
unsigned int odt_wr_cfg;
|
||||
unsigned int odt_rtt_norm;
|
||||
unsigned int odt_rtt_wr;
|
||||
};
|
||||
|
||||
#ifndef CONFIG_STATIC_DDR
|
||||
#if defined(PHY_GEN2_FW_IMAGE_BUFFER) && !defined(NXP_DDR_PHY_GEN2)
|
||||
#error Missing NXP_DDR_PHY_GEN2
|
||||
#endif
|
||||
#ifdef NXP_DDR_PHY_GEN2
|
||||
static const struct dynamic_odt single_D[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_NEVER,
|
||||
DDR4_RTT_OFF,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt single_S[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{},
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_DD[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_60_OHM,
|
||||
DDR4_RTT_WR_240_OHM
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_60_OHM,
|
||||
DDR4_RTT_WR_240_OHM
|
||||
},
|
||||
{ /* cs2 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_60_OHM,
|
||||
DDR4_RTT_WR_240_OHM
|
||||
},
|
||||
{ /* cs3 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_60_OHM,
|
||||
DDR4_RTT_WR_240_OHM
|
||||
}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_SS[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{ /* cs2 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_D0[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_SAME_DIMM,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_NEVER,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_S0[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_CS,
|
||||
DDR4_RTT_80_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
#else
|
||||
static const struct dynamic_odt single_D[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_40_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_NEVER,
|
||||
DDR4_RTT_OFF,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt single_S[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_40_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{},
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_DD[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_SAME_DIMM,
|
||||
DDR4_RTT_120_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR4_RTT_34_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs2 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_SAME_DIMM,
|
||||
DDR4_RTT_120_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs3 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR4_RTT_34_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_SS[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_34_OHM,
|
||||
DDR4_RTT_WR_120_OHM
|
||||
},
|
||||
{},
|
||||
{ /* cs2 */
|
||||
DDR_ODT_OTHER_DIMM,
|
||||
DDR_ODT_ALL,
|
||||
DDR4_RTT_34_OHM,
|
||||
DDR4_RTT_WR_120_OHM
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_D0[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_SAME_DIMM,
|
||||
DDR4_RTT_40_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{ /* cs1 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_NEVER,
|
||||
DDR4_RTT_OFF,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dynamic_odt dual_S0[4] = {
|
||||
{ /* cs0 */
|
||||
DDR_ODT_NEVER,
|
||||
DDR_ODT_CS,
|
||||
DDR4_RTT_40_OHM,
|
||||
DDR4_RTT_WR_OFF
|
||||
},
|
||||
{},
|
||||
{},
|
||||
{}
|
||||
};
|
||||
#endif /* NXP_DDR_PHY_GEN2 */
|
||||
|
||||
/*
|
||||
* Automatically select bank interleaving mode based on DIMMs
|
||||
* in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
|
||||
* This function only deal with one or two slots per controller.
|
||||
*/
|
||||
static inline unsigned int auto_bank_intlv(const int cs_in_use,
|
||||
const struct dimm_params *pdimm)
|
||||
{
|
||||
switch (cs_in_use) {
|
||||
case 0xf:
|
||||
return DDR_BA_INTLV_CS0123;
|
||||
case 0x3:
|
||||
return DDR_BA_INTLV_CS01;
|
||||
case 0x1:
|
||||
return DDR_BA_NONE;
|
||||
case 0x5:
|
||||
return DDR_BA_NONE;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0U;
|
||||
}
|
||||
|
||||
static int cal_odt(const unsigned int clk,
|
||||
struct memctl_opt *popts,
|
||||
struct ddr_conf *conf,
|
||||
struct dimm_params *pdimm,
|
||||
const int dimm_slot_per_ctrl)
|
||||
|
||||
{
|
||||
unsigned int i;
|
||||
const struct dynamic_odt *pdodt = NULL;
|
||||
|
||||
const static struct dynamic_odt *table[2][5] = {
|
||||
{single_S, single_D, NULL, NULL},
|
||||
{dual_SS, dual_DD, NULL, NULL},
|
||||
};
|
||||
|
||||
if (dimm_slot_per_ctrl != 1 && dimm_slot_per_ctrl != 2) {
|
||||
ERROR("Unsupported number of DIMMs\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdodt = table[dimm_slot_per_ctrl - 1][pdimm->n_ranks - 1];
|
||||
if (pdodt == dual_SS) {
|
||||
pdodt = (conf->cs_in_use == 0x5) ? dual_SS :
|
||||
((conf->cs_in_use == 0x1) ? dual_S0 : NULL);
|
||||
} else if (pdodt == dual_DD) {
|
||||
pdodt = (conf->cs_in_use == 0xf) ? dual_DD :
|
||||
((conf->cs_in_use == 0x3) ? dual_D0 : NULL);
|
||||
}
|
||||
if (pdodt == dual_DD && pdimm->package_3ds) {
|
||||
ERROR("Too many 3DS DIMMs.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (pdodt == NULL) {
|
||||
ERROR("Error determing ODT.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Pick chip-select local options. */
|
||||
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
||||
debug("cs %d\n", i);
|
||||
popts->cs_odt[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
|
||||
debug(" odt_rd_cfg 0x%x\n",
|
||||
popts->cs_odt[i].odt_rd_cfg);
|
||||
popts->cs_odt[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
|
||||
debug(" odt_wr_cfg 0x%x\n",
|
||||
popts->cs_odt[i].odt_wr_cfg);
|
||||
popts->cs_odt[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
|
||||
debug(" odt_rtt_norm 0x%x\n",
|
||||
popts->cs_odt[i].odt_rtt_norm);
|
||||
popts->cs_odt[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
|
||||
debug(" odt_rtt_wr 0x%x\n",
|
||||
popts->cs_odt[i].odt_rtt_wr);
|
||||
popts->cs_odt[i].auto_precharge = 0;
|
||||
debug(" auto_precharge %d\n",
|
||||
popts->cs_odt[i].auto_precharge);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cal_opts(const unsigned int clk,
|
||||
struct memctl_opt *popts,
|
||||
struct ddr_conf *conf,
|
||||
struct dimm_params *pdimm,
|
||||
const int dimm_slot_per_ctrl,
|
||||
const unsigned int ip_rev)
|
||||
{
|
||||
popts->rdimm = pdimm->rdimm;
|
||||
popts->mirrored_dimm = pdimm->mirrored_dimm;
|
||||
#ifdef CONFIG_DDR_ECC_EN
|
||||
popts->ecc_mode = pdimm->edc_config == 0x02 ? 1 : 0;
|
||||
#endif
|
||||
popts->ctlr_init_ecc = popts->ecc_mode;
|
||||
debug("ctlr_init_ecc %d\n", popts->ctlr_init_ecc);
|
||||
popts->self_refresh_in_sleep = 1;
|
||||
popts->dynamic_power = 0;
|
||||
|
||||
/*
|
||||
* check sdram width, allow platform override
|
||||
* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
|
||||
*/
|
||||
if (pdimm->primary_sdram_width == 64) {
|
||||
popts->data_bus_dimm = DDR_DBUS_64;
|
||||
popts->otf_burst_chop_en = 1;
|
||||
} else if (pdimm->primary_sdram_width == 32) {
|
||||
popts->data_bus_dimm = DDR_DBUS_32;
|
||||
popts->otf_burst_chop_en = 0;
|
||||
} else if (pdimm->primary_sdram_width == 16) {
|
||||
popts->data_bus_dimm = DDR_DBUS_16;
|
||||
popts->otf_burst_chop_en = 0;
|
||||
} else {
|
||||
ERROR("primary sdram width invalid!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
popts->data_bus_used = popts->data_bus_dimm;
|
||||
popts->x4_en = (pdimm->device_width == 4) ? 1 : 0;
|
||||
debug("x4_en %d\n", popts->x4_en);
|
||||
|
||||
/* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
|
||||
if (popts->rdimm != 0) {
|
||||
popts->ap_en = 1; /* 0 = disable, 1 = enable */
|
||||
} else {
|
||||
popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
|
||||
}
|
||||
|
||||
if (ip_rev == 0x50500) {
|
||||
popts->ap_en = 0;
|
||||
}
|
||||
|
||||
debug("ap_en %d\n", popts->ap_en);
|
||||
|
||||
/* BSTTOPRE precharge interval uses 1/4 of refint value. */
|
||||
popts->bstopre = picos_to_mclk(clk, pdimm->refresh_rate_ps) >> 2;
|
||||
popts->tfaw_ps = pdimm->tfaw_ps;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cal_intlv(const int num_ctlrs,
|
||||
struct memctl_opt *popts,
|
||||
struct ddr_conf *conf,
|
||||
struct dimm_params *pdimm)
|
||||
{
|
||||
#ifdef NXP_DDR_INTLV_256B
|
||||
if (num_ctlrs == 2) {
|
||||
popts->ctlr_intlv = 1;
|
||||
popts->ctlr_intlv_mode = DDR_256B_INTLV;
|
||||
}
|
||||
#endif
|
||||
debug("ctlr_intlv %d\n", popts->ctlr_intlv);
|
||||
debug("ctlr_intlv_mode %d\n", popts->ctlr_intlv_mode);
|
||||
|
||||
popts->ba_intlv = auto_bank_intlv(conf->cs_in_use, pdimm);
|
||||
debug("ba_intlv 0x%x\n", popts->ba_intlv);
|
||||
}
|
||||
|
||||
static int update_burst_length(struct memctl_opt *popts)
|
||||
{
|
||||
/* Choose burst length. */
|
||||
if ((popts->data_bus_used == DDR_DBUS_32) ||
|
||||
(popts->data_bus_used == DDR_DBUS_16)) {
|
||||
/* 32-bit or 16-bit bus */
|
||||
popts->otf_burst_chop_en = 0;
|
||||
popts->burst_length = DDR_BL8;
|
||||
} else if (popts->otf_burst_chop_en != 0) { /* on-the-fly burst chop */
|
||||
popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
|
||||
} else {
|
||||
popts->burst_length = DDR_BL8;
|
||||
}
|
||||
debug("data_bus_used %d\n", popts->data_bus_used);
|
||||
debug("otf_burst_chop_en %d\n", popts->otf_burst_chop_en);
|
||||
debug("burst_length 0x%x\n", popts->burst_length);
|
||||
/*
|
||||
* If a reduced data width is requested, but the SPD
|
||||
* specifies a physically wider device, adjust the
|
||||
* computed dimm capacities accordingly before
|
||||
* assigning addresses.
|
||||
* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
|
||||
*/
|
||||
if (popts->data_bus_dimm > popts->data_bus_used) {
|
||||
ERROR("Data bus configuration error\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
popts->dbw_cap_shift = popts->data_bus_used - popts->data_bus_dimm;
|
||||
debug("dbw_cap_shift %d\n", popts->dbw_cap_shift);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cal_board_params(struct ddr_info *priv,
|
||||
const struct board_timing *dimm,
|
||||
int len)
|
||||
{
|
||||
const unsigned long speed = priv->clk / 1000000;
|
||||
const struct dimm_params *pdimm = &priv->dimm;
|
||||
struct memctl_opt *popts = &priv->opt;
|
||||
struct rc_timing const *prt = NULL;
|
||||
struct rc_timing const *chosen = NULL;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (pdimm->rc == dimm[i].rc) {
|
||||
prt = dimm[i].p;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (prt == NULL) {
|
||||
ERROR("Board parameters no match.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
while (prt->speed_bin != 0) {
|
||||
if (speed <= prt->speed_bin) {
|
||||
chosen = prt;
|
||||
break;
|
||||
}
|
||||
prt++;
|
||||
}
|
||||
if (chosen == NULL) {
|
||||
ERROR("timing no match for speed %lu\n", speed);
|
||||
return -EINVAL;
|
||||
}
|
||||
popts->clk_adj = prt->clk_adj;
|
||||
popts->wrlvl_start = prt->wrlvl;
|
||||
popts->wrlvl_ctl_2 = (prt->wrlvl * 0x01010101 + dimm[i].add1) &
|
||||
0xFFFFFFFF;
|
||||
popts->wrlvl_ctl_3 = (prt->wrlvl * 0x01010101 + dimm[i].add2) &
|
||||
0xFFFFFFFF;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int synthesize_ctlr(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = cal_odt(priv->clk,
|
||||
&priv->opt,
|
||||
&priv->conf,
|
||||
&priv->dimm,
|
||||
priv->dimm_on_ctlr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = cal_opts(priv->clk,
|
||||
&priv->opt,
|
||||
&priv->conf,
|
||||
&priv->dimm,
|
||||
priv->dimm_on_ctlr,
|
||||
priv->ip_rev);
|
||||
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
cal_intlv(priv->num_ctlrs, &priv->opt, &priv->conf, &priv->dimm);
|
||||
ret = ddr_board_options(priv);
|
||||
if (ret != 0) {
|
||||
ERROR("Failed matching board timing.\n");
|
||||
}
|
||||
|
||||
ret = update_burst_length(&priv->opt);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Return the bit mask of valid DIMMs found */
|
||||
static int parse_spd(struct ddr_info *priv)
|
||||
{
|
||||
struct ddr_conf *conf = &priv->conf;
|
||||
struct dimm_params *dimm = &priv->dimm;
|
||||
int j, valid_mask = 0;
|
||||
|
||||
#ifdef CONFIG_DDR_NODIMM
|
||||
valid_mask = ddr_get_ddr_params(dimm, conf);
|
||||
if (valid_mask < 0) {
|
||||
ERROR("DDR params error\n");
|
||||
return valid_mask;
|
||||
}
|
||||
#else
|
||||
const int *spd_addr = priv->spd_addr;
|
||||
const int num_ctlrs = priv->num_ctlrs;
|
||||
const int num_dimm = priv->dimm_on_ctlr;
|
||||
struct ddr4_spd spd[2];
|
||||
unsigned int spd_checksum[2];
|
||||
int addr_idx = 0;
|
||||
int spd_idx = 0;
|
||||
int ret, addr, i;
|
||||
|
||||
/* Scan all DIMMs */
|
||||
for (i = 0; i < num_ctlrs; i++) {
|
||||
debug("Controller %d\n", i);
|
||||
for (j = 0; j < num_dimm; j++, addr_idx++) {
|
||||
debug("DIMM %d\n", j);
|
||||
addr = spd_addr[addr_idx];
|
||||
if (addr == 0) {
|
||||
if (j == 0) {
|
||||
ERROR("First SPD addr wrong.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
debug("addr 0x%x\n", addr);
|
||||
ret = read_spd(addr, &spd[spd_idx],
|
||||
sizeof(struct ddr4_spd));
|
||||
if (ret != 0) { /* invalid */
|
||||
debug("Invalid SPD at address 0x%x\n", addr);
|
||||
continue;
|
||||
}
|
||||
|
||||
spd_checksum[spd_idx] =
|
||||
(spd[spd_idx].crc[1] << 24) |
|
||||
(spd[spd_idx].crc[0] << 16) |
|
||||
(spd[spd_idx].mod_section.uc[127] << 8) |
|
||||
(spd[spd_idx].mod_section.uc[126] << 0);
|
||||
debug("checksum 0x%x\n", spd_checksum[spd_idx]);
|
||||
if (spd_checksum[spd_idx] == 0) {
|
||||
debug("Bad checksum, ignored.\n");
|
||||
continue;
|
||||
}
|
||||
if (spd_idx == 0) {
|
||||
/* first valid SPD */
|
||||
ret = cal_dimm_params(&spd[0], dimm);
|
||||
if (ret != 0) {
|
||||
ERROR("SPD calculation error\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if (spd_idx != 0 && spd_checksum[0] !=
|
||||
spd_checksum[spd_idx]) {
|
||||
ERROR("Not identical DIMMs.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
conf->dimm_in_use[j] = 1;
|
||||
valid_mask |= 1 << addr_idx;
|
||||
spd_idx = 1;
|
||||
}
|
||||
debug("done with controller %d\n", i);
|
||||
}
|
||||
switch (num_ctlrs) {
|
||||
case 1:
|
||||
if ((valid_mask & 0x1) == 0) {
|
||||
ERROR("First slot cannot be empty.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
switch (num_dimm) {
|
||||
case 1:
|
||||
if (valid_mask == 0) {
|
||||
ERROR("Both slot empty\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (valid_mask != 0x5 &&
|
||||
valid_mask != 0xf &&
|
||||
(valid_mask & 0x7) != 0x4 &&
|
||||
(valid_mask & 0xd) != 0x1) {
|
||||
ERROR("Invalid DIMM combination.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ERROR("Invalid number of DIMMs.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ERROR("Invalid number of controllers.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
/* now we have valid and identical DIMMs on controllers */
|
||||
#endif /* CONFIG_DDR_NODIMM */
|
||||
|
||||
debug("cal cs\n");
|
||||
conf->cs_in_use = 0;
|
||||
for (j = 0; j < DDRC_NUM_DIMM; j++) {
|
||||
if (conf->dimm_in_use[j] == 0) {
|
||||
continue;
|
||||
}
|
||||
switch (dimm->n_ranks) {
|
||||
case 4:
|
||||
ERROR("Quad-rank DIMM not supported\n");
|
||||
return -EINVAL;
|
||||
case 2:
|
||||
conf->cs_on_dimm[j] = 0x3 << (j * CONFIG_CS_PER_SLOT);
|
||||
conf->cs_in_use |= conf->cs_on_dimm[j];
|
||||
break;
|
||||
case 1:
|
||||
conf->cs_on_dimm[j] = 0x1 << (j * CONFIG_CS_PER_SLOT);
|
||||
conf->cs_in_use |= conf->cs_on_dimm[j];
|
||||
break;
|
||||
default:
|
||||
ERROR("SPD error with n_ranks\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
debug("cs_in_use = %x\n", conf->cs_in_use);
|
||||
debug("cs_on_dimm[%d] = %x\n", j, conf->cs_on_dimm[j]);
|
||||
}
|
||||
#ifndef CONFIG_DDR_NODIMM
|
||||
if (priv->dimm.rdimm != 0) {
|
||||
NOTICE("RDIMM %s\n", priv->dimm.mpart);
|
||||
} else {
|
||||
NOTICE("UDIMM %s\n", priv->dimm.mpart);
|
||||
}
|
||||
#else
|
||||
NOTICE("%s\n", priv->dimm.mpart);
|
||||
#endif
|
||||
|
||||
return valid_mask;
|
||||
}
|
||||
|
||||
static unsigned long long assign_intlv_addr(
|
||||
const struct dimm_params *pdimm,
|
||||
const struct memctl_opt *opt,
|
||||
struct ddr_conf *conf,
|
||||
const unsigned long long current_mem_base)
|
||||
{
|
||||
int i;
|
||||
int ctlr_density_mul = 0;
|
||||
const unsigned long long rank_density = pdimm->rank_density >>
|
||||
opt->dbw_cap_shift;
|
||||
unsigned long long total_ctlr_mem;
|
||||
|
||||
debug("rank density 0x%llx\n", rank_density);
|
||||
switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
|
||||
case DDR_BA_INTLV_CS0123:
|
||||
ctlr_density_mul = 4;
|
||||
break;
|
||||
case DDR_BA_INTLV_CS01:
|
||||
ctlr_density_mul = 2;
|
||||
break;
|
||||
default:
|
||||
ctlr_density_mul = 1;
|
||||
break;
|
||||
}
|
||||
debug("ctlr density mul %d\n", ctlr_density_mul);
|
||||
switch (opt->ctlr_intlv_mode) {
|
||||
case DDR_256B_INTLV:
|
||||
total_ctlr_mem = 2 * ctlr_density_mul * rank_density;
|
||||
break;
|
||||
default:
|
||||
ERROR("Unknown interleaving mode");
|
||||
return 0;
|
||||
}
|
||||
conf->base_addr = current_mem_base;
|
||||
conf->total_mem = total_ctlr_mem;
|
||||
|
||||
/* overwrite cs_in_use bitmask with controller interleaving */
|
||||
conf->cs_in_use = (1 << ctlr_density_mul) - 1;
|
||||
debug("Overwrite cs_in_use as %x\n", conf->cs_in_use);
|
||||
|
||||
/* Fill addr with each cs in use */
|
||||
for (i = 0; i < ctlr_density_mul; i++) {
|
||||
conf->cs_base_addr[i] = current_mem_base;
|
||||
conf->cs_size[i] = total_ctlr_mem;
|
||||
debug("CS %d\n", i);
|
||||
debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
|
||||
debug(" size 0x%llx\n", conf->cs_size[i]);
|
||||
}
|
||||
|
||||
return total_ctlr_mem;
|
||||
}
|
||||
|
||||
static unsigned long long assign_non_intlv_addr(
|
||||
const struct dimm_params *pdimm,
|
||||
const struct memctl_opt *opt,
|
||||
struct ddr_conf *conf,
|
||||
unsigned long long current_mem_base)
|
||||
{
|
||||
int i;
|
||||
const unsigned long long rank_density = pdimm->rank_density >>
|
||||
opt->dbw_cap_shift;
|
||||
unsigned long long total_ctlr_mem = 0ULL;
|
||||
|
||||
debug("rank density 0x%llx\n", rank_density);
|
||||
conf->base_addr = current_mem_base;
|
||||
|
||||
/* assign each cs */
|
||||
switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
|
||||
case DDR_BA_INTLV_CS0123:
|
||||
for (i = 0; i < DDRC_NUM_CS; i++) {
|
||||
conf->cs_base_addr[i] = current_mem_base;
|
||||
conf->cs_size[i] = rank_density << 2;
|
||||
total_ctlr_mem += rank_density;
|
||||
}
|
||||
break;
|
||||
case DDR_BA_INTLV_CS01:
|
||||
for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) && i < 2; i++) {
|
||||
conf->cs_base_addr[i] = current_mem_base;
|
||||
conf->cs_size[i] = rank_density << 1;
|
||||
total_ctlr_mem += rank_density;
|
||||
}
|
||||
current_mem_base += total_ctlr_mem;
|
||||
for (; ((conf->cs_in_use & (1 << i)) != 0) && i < DDRC_NUM_CS;
|
||||
i++) {
|
||||
conf->cs_base_addr[i] = current_mem_base;
|
||||
conf->cs_size[i] = rank_density;
|
||||
total_ctlr_mem += rank_density;
|
||||
current_mem_base += rank_density;
|
||||
}
|
||||
break;
|
||||
case DDR_BA_NONE:
|
||||
for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
|
||||
(i < DDRC_NUM_CS); i++) {
|
||||
conf->cs_base_addr[i] = current_mem_base;
|
||||
conf->cs_size[i] = rank_density;
|
||||
current_mem_base += rank_density;
|
||||
total_ctlr_mem += rank_density;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ERROR("Unsupported bank interleaving\n");
|
||||
return 0;
|
||||
}
|
||||
for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
|
||||
(i < DDRC_NUM_CS); i++) {
|
||||
debug("CS %d\n", i);
|
||||
debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
|
||||
debug(" size 0x%llx\n", conf->cs_size[i]);
|
||||
}
|
||||
|
||||
return total_ctlr_mem;
|
||||
}
|
||||
|
||||
unsigned long long assign_addresses(struct ddr_info *priv)
|
||||
__attribute__ ((weak));
|
||||
|
||||
unsigned long long assign_addresses(struct ddr_info *priv)
|
||||
{
|
||||
struct memctl_opt *opt = &priv->opt;
|
||||
const struct dimm_params *dimm = &priv->dimm;
|
||||
struct ddr_conf *conf = &priv->conf;
|
||||
unsigned long long current_mem_base = priv->mem_base;
|
||||
unsigned long long total_mem;
|
||||
|
||||
total_mem = 0ULL;
|
||||
debug("ctlr_intlv %d\n", opt->ctlr_intlv);
|
||||
if (opt->ctlr_intlv != 0) {
|
||||
total_mem = assign_intlv_addr(dimm, opt, conf,
|
||||
current_mem_base);
|
||||
} else {
|
||||
/*
|
||||
* Simple linear assignment if memory controllers are not
|
||||
* interleaved. This is only valid for SoCs with single DDRC.
|
||||
*/
|
||||
total_mem = assign_non_intlv_addr(dimm, opt, conf,
|
||||
current_mem_base);
|
||||
}
|
||||
conf->total_mem = total_mem;
|
||||
debug("base 0x%llx\n", current_mem_base);
|
||||
debug("Total mem by assignment is 0x%llx\n", total_mem);
|
||||
|
||||
return total_mem;
|
||||
}
|
||||
|
||||
static int cal_ddrc_regs(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = compute_ddrc(priv->clk,
|
||||
&priv->opt,
|
||||
&priv->conf,
|
||||
&priv->ddr_reg,
|
||||
&priv->dimm,
|
||||
priv->ip_rev);
|
||||
if (ret != 0) {
|
||||
ERROR("Calculating DDR registers failed\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STATIC_DDR */
|
||||
|
||||
static int write_ddrc_regs(struct ddr_info *priv)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < priv->num_ctlrs; i++) {
|
||||
ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0);
|
||||
if (ret != 0) {
|
||||
ERROR("Writing DDR register(s) failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long long dram_init(struct ddr_info *priv
|
||||
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
|
||||
, uintptr_t nxp_ccn_hn_f0_addr
|
||||
#endif
|
||||
)
|
||||
{
|
||||
uint64_t time __unused;
|
||||
long long dram_size;
|
||||
int ret;
|
||||
const uint64_t time_base = get_timer_val(0);
|
||||
unsigned int ip_rev = get_ddrc_version(priv->ddr[0]);
|
||||
|
||||
int valid_spd_mask __unused;
|
||||
int scratch = 0x0;
|
||||
|
||||
priv->ip_rev = ip_rev;
|
||||
|
||||
#ifndef CONFIG_STATIC_DDR
|
||||
INFO("time base %llu ms\n", time_base);
|
||||
debug("Parse DIMM SPD(s)\n");
|
||||
valid_spd_mask = parse_spd(priv);
|
||||
|
||||
if (valid_spd_mask < 0) {
|
||||
ERROR("Parsing DIMM Error\n");
|
||||
return valid_spd_mask;
|
||||
}
|
||||
|
||||
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
|
||||
if (priv->num_ctlrs == 2 || priv->num_ctlrs == 1) {
|
||||
ret = disable_unused_ddrc(priv, valid_spd_mask,
|
||||
nxp_ccn_hn_f0_addr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
time = get_timer_val(time_base);
|
||||
INFO("Time after parsing SPD %llu ms\n", time);
|
||||
debug("Synthesize configurations\n");
|
||||
ret = synthesize_ctlr(priv);
|
||||
if (ret != 0) {
|
||||
ERROR("Synthesize config error\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
debug("Assign binding addresses\n");
|
||||
dram_size = assign_addresses(priv);
|
||||
if (dram_size == 0) {
|
||||
ERROR("Assigning address error\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
debug("Calculate controller registers\n");
|
||||
ret = cal_ddrc_regs(priv);
|
||||
if (ret != 0) {
|
||||
ERROR("Calculate register error\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = compute_ddr_phy(priv);
|
||||
if (ret != 0)
|
||||
ERROR("Calculating DDR PHY registers failed.\n");
|
||||
|
||||
#else
|
||||
dram_size = board_static_ddr(priv);
|
||||
if (dram_size == 0) {
|
||||
ERROR("Error getting static DDR settings.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (priv->warm_boot_flag == DDR_WARM_BOOT) {
|
||||
scratch = (priv->ddr_reg).sdram_cfg[1];
|
||||
scratch = scratch & ~(SDRAM_CFG2_D_INIT);
|
||||
priv->ddr_reg.sdram_cfg[1] = scratch;
|
||||
}
|
||||
|
||||
time = get_timer_val(time_base);
|
||||
INFO("Time before programming controller %llu ms\n", time);
|
||||
debug("Program controller registers\n");
|
||||
ret = write_ddrc_regs(priv);
|
||||
if (ret != 0) {
|
||||
ERROR("Programing DDRC error\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
puts("");
|
||||
NOTICE("%lld GB ", dram_size >> 30);
|
||||
print_ddr_info(priv->ddr[0]);
|
||||
|
||||
time = get_timer_val(time_base);
|
||||
INFO("Time used by DDR driver %llu ms\n", time);
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
#
|
||||
# Copyright 2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
DDR_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ddr
|
||||
|
||||
ifeq ($(PLAT_DDR_PHY), PHY_GEN2)
|
||||
$(eval $(call add_define, PHY_GEN2))
|
||||
PLAT_DDR_PHY_DIR := phy-gen2
|
||||
ifeq (${APPLY_MAX_CDD},yes)
|
||||
$(eval $(call add_define,NXP_APPLY_MAX_CDD))
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_DDR_A011396}, 1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A011396))
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_DDR_A050450}, 1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A050450))
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(PLAT_DDR_PHY), PHY_GEN1)
|
||||
PLAT_DDR_PHY_DIR := phy-gen1
|
||||
|
||||
ifeq (${ERRATA_DDR_A008511},1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A008511))
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_DDR_A009803},1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A009803))
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_DDR_A009942},1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A009942))
|
||||
endif
|
||||
|
||||
ifeq (${ERRATA_DDR_A010165},1)
|
||||
$(eval $(call add_define,ERRATA_DDR_A010165))
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(DDR_BIST), yes)
|
||||
$(eval $(call add_define, BIST_EN))
|
||||
endif
|
||||
|
||||
ifeq ($(DDR_DEBUG), yes)
|
||||
$(eval $(call add_define, DDR_DEBUG))
|
||||
endif
|
||||
|
||||
ifeq ($(DDR_PHY_DEBUG), yes)
|
||||
$(eval $(call add_define, DDR_PHY_DEBUG))
|
||||
endif
|
||||
|
||||
ifeq ($(DEBUG_PHY_IO), yes)
|
||||
$(eval $(call add_define, DEBUG_PHY_IO))
|
||||
endif
|
||||
|
||||
ifeq ($(DEBUG_WARM_RESET), yes)
|
||||
$(eval $(call add_define, DEBUG_WARM_RESET))
|
||||
endif
|
||||
|
||||
ifeq ($(DEBUG_DDR_INPUT_CONFIG), yes)
|
||||
$(eval $(call add_define, DEBUG_DDR_INPUT_CONFIG))
|
||||
endif
|
||||
|
||||
DDR_CNTLR_SOURCES := $(DDR_DRIVERS_PATH)/nxp-ddr/ddr.c \
|
||||
$(DDR_DRIVERS_PATH)/nxp-ddr/ddrc.c \
|
||||
$(DDR_DRIVERS_PATH)/nxp-ddr/dimm.c \
|
||||
$(DDR_DRIVERS_PATH)/nxp-ddr/regs.c \
|
||||
$(DDR_DRIVERS_PATH)/nxp-ddr/utility.c \
|
||||
$(DDR_DRIVERS_PATH)/$(PLAT_DDR_PHY_DIR)/phy.c
|
||||
|
||||
PLAT_INCLUDES += -I$(DDR_DRIVERS_PATH)/nxp-ddr \
|
||||
-I$(DDR_DRIVERS_PATH)/include
|
||||
|
|
@ -0,0 +1,594 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <immap.h>
|
||||
|
||||
#define BIST_CR 0x80060000
|
||||
#define BIST_CR_EN 0x80000000
|
||||
#define BIST_CR_STAT 0x00000001
|
||||
#define CTLR_INTLV_MASK 0x20000000
|
||||
|
||||
#pragma weak run_bist
|
||||
|
||||
bool run_bist(void)
|
||||
{
|
||||
#ifdef BIST_EN
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Perform build-in test on memory
|
||||
* timeout value in 10ms
|
||||
*/
|
||||
int bist(const struct ccsr_ddr *ddr, int timeout)
|
||||
{
|
||||
const unsigned int test_pattern[10] = {
|
||||
0xffffffff,
|
||||
0x00000000,
|
||||
0xaaaaaaaa,
|
||||
0x55555555,
|
||||
0xcccccccc,
|
||||
0x33333333,
|
||||
0x12345678,
|
||||
0xabcdef01,
|
||||
0xaa55aa55,
|
||||
0x55aa55aa
|
||||
};
|
||||
unsigned int mtcr, err_detect, err_sbe;
|
||||
unsigned int cs0_config;
|
||||
unsigned int csn_bnds[4];
|
||||
int ret = 0;
|
||||
uint32_t i;
|
||||
#ifdef CONFIG_DDR_ADDR_DEC
|
||||
uint32_t dec_9 = ddr_in32(&ddr->dec[9]);
|
||||
uint32_t pos = 0U;
|
||||
uint32_t map_save = 0U;
|
||||
uint32_t temp32 = 0U;
|
||||
uint32_t map, shift, highest;
|
||||
#endif
|
||||
|
||||
cs0_config = ddr_in32(&ddr->csn_cfg[0]);
|
||||
if ((cs0_config & CTLR_INTLV_MASK) != 0U) {
|
||||
/* set bnds to non-interleaving */
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
csn_bnds[i] = ddr_in32(&ddr->bnds[i].a);
|
||||
ddr_out32(&ddr->bnds[i].a,
|
||||
(csn_bnds[i] & U(0xfffefffe)) >> 1U);
|
||||
}
|
||||
ddr_out32(&ddr->csn_cfg[0], cs0_config & ~CTLR_INTLV_MASK);
|
||||
#ifdef CONFIG_DDR_ADDR_DEC
|
||||
if ((dec_9 & 0x1U) != 0U) {
|
||||
highest = (dec_9 >> 26U) == U(0x3F) ? 0U : dec_9 >> 26U;
|
||||
pos = 37U;
|
||||
for (i = 0U; i < 36U; i++) { /* Go through all 37 */
|
||||
if ((i % 4U) == 0U) {
|
||||
temp32 = ddr_in32(&ddr->dec[i >> 2U]);
|
||||
}
|
||||
shift = (3U - i % 4U) * 8U + 2U;
|
||||
map = (temp32 >> shift) & U(0x3F);
|
||||
if (map > highest && map != U(0x3F)) {
|
||||
highest = map;
|
||||
pos = i;
|
||||
}
|
||||
}
|
||||
debug("\nFound highest position %d, mapping to %d, ",
|
||||
pos, highest);
|
||||
map_save = ddr_in32(&ddr->dec[pos >> 2]);
|
||||
shift = (3U - pos % 4U) * 8U + 2U;
|
||||
debug("in dec[%d], bit %d (0x%x)\n",
|
||||
pos >> 2U, shift, map_save);
|
||||
temp32 = map_save & ~(U(0x3F) << shift);
|
||||
temp32 |= 8U << shift;
|
||||
ddr_out32(&ddr->dec[pos >> 2U], temp32);
|
||||
timeout <<= 2U;
|
||||
debug("Increase wait time to %d ms\n", timeout * 10);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
for (i = 0U; i < 10U; i++) {
|
||||
ddr_out32(&ddr->mtp[i], test_pattern[i]);
|
||||
}
|
||||
mtcr = BIST_CR;
|
||||
ddr_out32(&ddr->mtcr, mtcr);
|
||||
do {
|
||||
mdelay(10);
|
||||
mtcr = ddr_in32(&ddr->mtcr);
|
||||
} while (timeout-- > 0 && ((mtcr & BIST_CR_EN) != 0));
|
||||
if (timeout <= 0) {
|
||||
ERROR("Timeout\n");
|
||||
} else {
|
||||
debug("Timer remains %d\n", timeout);
|
||||
}
|
||||
|
||||
err_detect = ddr_in32(&ddr->err_detect);
|
||||
err_sbe = ddr_in32(&ddr->err_sbe);
|
||||
if (err_detect != 0U || ((err_sbe & U(0xffff)) != 0U)) {
|
||||
ERROR("ECC error detected\n");
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
if ((cs0_config & CTLR_INTLV_MASK) != 0) {
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
ddr_out32(&ddr->bnds[i].a, csn_bnds[i]);
|
||||
}
|
||||
ddr_out32(&ddr->csn_cfg[0], cs0_config);
|
||||
#ifdef CONFIG_DDR_ADDR_DEC
|
||||
if ((dec_9 & U(0x1)) != 0U) {
|
||||
ddr_out32(&ddr->dec[pos >> 2], map_save);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
if ((mtcr & BIST_CR_STAT) != 0) {
|
||||
ERROR("Built-in self test failed\n");
|
||||
ret = -EIO;
|
||||
} else {
|
||||
NOTICE("Build-in self test passed\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void dump_ddrc(unsigned int *ddr)
|
||||
{
|
||||
#ifdef DDR_DEBUG
|
||||
uint32_t i;
|
||||
unsigned long val;
|
||||
|
||||
for (i = 0U; i < U(0x400); i++, ddr++) {
|
||||
val = ddr_in32(ddr);
|
||||
if (val != 0U) { /* skip zeros */
|
||||
debug("*0x%lx = 0x%lx\n", (unsigned long)ddr, val);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef ERRATA_DDR_A009803
|
||||
static void set_wait_for_bits_clear(const void *ptr,
|
||||
unsigned int value,
|
||||
unsigned int bits)
|
||||
{
|
||||
int timeout = 1000;
|
||||
|
||||
ddr_out32(ptr, value);
|
||||
do {
|
||||
udelay(100);
|
||||
} while (timeout-- > 0 && ((ddr_in32(ptr) & bits) != 0));
|
||||
|
||||
if (timeout <= 0) {
|
||||
ERROR("wait for clear timeout.\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (DDRC_NUM_CS > 4)
|
||||
#error Invalid setting for DDRC_NUM_CS
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If supported by the platform, writing to DDR controller takes two
|
||||
* passes to deassert DDR reset to comply with JEDEC specs for RDIMMs.
|
||||
*/
|
||||
int ddrc_set_regs(const unsigned long clk,
|
||||
const struct ddr_cfg_regs *regs,
|
||||
const struct ccsr_ddr *ddr,
|
||||
int twopass)
|
||||
{
|
||||
unsigned int i, bus_width;
|
||||
unsigned int temp_sdram_cfg;
|
||||
unsigned int total_mem_per_ctrl, total_mem_per_ctrl_adj;
|
||||
const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
|
||||
int timeout;
|
||||
int ret = 0;
|
||||
#if defined(ERRATA_DDR_A009942) || defined(ERRATA_DDR_A010165)
|
||||
unsigned long ddr_freq;
|
||||
unsigned int tmp;
|
||||
#ifdef ERRATA_DDR_A009942
|
||||
unsigned int check;
|
||||
unsigned int cpo_min = U(0xff);
|
||||
unsigned int cpo_max = 0U;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (twopass == 2U) {
|
||||
goto after_reset;
|
||||
}
|
||||
|
||||
/* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
|
||||
ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]);
|
||||
|
||||
ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl);
|
||||
|
||||
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
||||
if (mod_bnds != 0U) {
|
||||
ddr_out32(&ddr->bnds[i].a,
|
||||
(regs->cs[i].bnds & U(0xfffefffe)) >> 1U);
|
||||
} else {
|
||||
ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
|
||||
}
|
||||
ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2);
|
||||
}
|
||||
|
||||
ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]);
|
||||
ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]);
|
||||
ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]);
|
||||
ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]);
|
||||
ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]);
|
||||
ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]);
|
||||
ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]);
|
||||
ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]);
|
||||
ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]);
|
||||
ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]);
|
||||
ddr_out32(&ddr->zq_cntl, regs->zq_cntl);
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
ddr_out32(&ddr->dq_map[i], regs->dq_map[i]);
|
||||
}
|
||||
ddr_out32(&ddr->sdram_cfg_3, regs->sdram_cfg[2]);
|
||||
ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]);
|
||||
ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]);
|
||||
ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]);
|
||||
ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]);
|
||||
ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]);
|
||||
ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]);
|
||||
ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]);
|
||||
ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]);
|
||||
ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]);
|
||||
ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]);
|
||||
ddr_out32(&ddr->sdram_mode_11, regs->sdram_mode[10]);
|
||||
ddr_out32(&ddr->sdram_mode_12, regs->sdram_mode[11]);
|
||||
ddr_out32(&ddr->sdram_mode_13, regs->sdram_mode[12]);
|
||||
ddr_out32(&ddr->sdram_mode_14, regs->sdram_mode[13]);
|
||||
ddr_out32(&ddr->sdram_mode_15, regs->sdram_mode[14]);
|
||||
ddr_out32(&ddr->sdram_mode_16, regs->sdram_mode[15]);
|
||||
ddr_out32(&ddr->sdram_md_cntl, regs->md_cntl);
|
||||
#ifdef ERRATA_DDR_A009663
|
||||
ddr_out32(&ddr->sdram_interval,
|
||||
regs->interval & ~SDRAM_INTERVAL_BSTOPRE);
|
||||
#else
|
||||
ddr_out32(&ddr->sdram_interval, regs->interval);
|
||||
#endif
|
||||
ddr_out32(&ddr->sdram_data_init, regs->data_init);
|
||||
if (regs->eor != 0) {
|
||||
ddr_out32(&ddr->eor, regs->eor);
|
||||
}
|
||||
|
||||
ddr_out32(&ddr->wrlvl_cntl, regs->wrlvl_cntl[0]);
|
||||
#ifndef NXP_DDR_EMU
|
||||
/*
|
||||
* Skip these two registers if running on emulator
|
||||
* because emulator doesn't have skew between bytes.
|
||||
*/
|
||||
|
||||
if (regs->wrlvl_cntl[1] != 0) {
|
||||
ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->wrlvl_cntl[1]);
|
||||
}
|
||||
if (regs->wrlvl_cntl[2] != 0) {
|
||||
ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->wrlvl_cntl[2]);
|
||||
}
|
||||
#endif
|
||||
|
||||
ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_1, regs->sdram_rcw[0]);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_2, regs->sdram_rcw[1]);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_3, regs->sdram_rcw[2]);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_4, regs->sdram_rcw[3]);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->sdram_rcw[4]);
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->sdram_rcw[5]);
|
||||
ddr_out32(&ddr->ddr_cdr2, regs->cdr[1]);
|
||||
ddr_out32(&ddr->sdram_cfg_2, regs->sdram_cfg[1]);
|
||||
ddr_out32(&ddr->init_addr, regs->init_addr);
|
||||
ddr_out32(&ddr->init_ext_addr, regs->init_ext_addr);
|
||||
|
||||
#ifdef ERRATA_DDR_A009803
|
||||
/* part 1 of 2 */
|
||||
if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
|
||||
if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
|
||||
ddr_out32(&ddr->ddr_sdram_rcw_2,
|
||||
regs->sdram_rcw[1] & ~0xf0);
|
||||
}
|
||||
|
||||
ddr_out32(&ddr->err_disable,
|
||||
regs->err_disable | DDR_ERR_DISABLE_APED);
|
||||
}
|
||||
#else
|
||||
ddr_out32(&ddr->err_disable, regs->err_disable);
|
||||
#endif
|
||||
ddr_out32(&ddr->err_int_en, regs->err_int_en);
|
||||
|
||||
/* For DDRC 5.05 only */
|
||||
if (get_ddrc_version(ddr) == 0x50500) {
|
||||
ddr_out32(&ddr->tx_cfg[1], 0x1f1f1f1f);
|
||||
ddr_out32(&ddr->debug[3], 0x124a02c0);
|
||||
}
|
||||
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
if (regs->tx_cfg[i] != 0) {
|
||||
ddr_out32(&ddr->tx_cfg[i], regs->tx_cfg[i]);
|
||||
}
|
||||
}
|
||||
for (i = 0U; i < 64U; i++) {
|
||||
if (regs->debug[i] != 0) {
|
||||
#ifdef ERRATA_DDR_A009942
|
||||
if (i == 28U) {
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
ddr_out32(&ddr->debug[i], regs->debug[i]);
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_DDR_ADDR_DEC
|
||||
if ((regs->dec[9] & 1) != 0U) {
|
||||
for (i = 0U; i < 10U; i++) {
|
||||
ddr_out32(&ddr->dec[i], regs->dec[i]);
|
||||
}
|
||||
if (mod_bnds != 0) {
|
||||
debug("Disable address decoding\n");
|
||||
ddr_out32(&ddr->dec[9], 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_DDR_A008511
|
||||
/* Part 1 of 2 */
|
||||
/* This erraum only applies to verion 5.2.1 */
|
||||
if (get_ddrc_version(ddr) == 0x50200) {
|
||||
ERROR("Unsupported SoC.\n");
|
||||
} else if (get_ddrc_version(ddr) == 0x50201) {
|
||||
ddr_out32(&ddr->debug[37], (U(1) << 31));
|
||||
ddr_out32(&ddr->ddr_cdr2,
|
||||
regs->cdr[1] | DDR_CDR2_VREF_TRAIN_EN);
|
||||
} else {
|
||||
debug("Erratum A008511 doesn't apply.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_DDR_A009942
|
||||
ddr_freq = clk / 1000000U;
|
||||
tmp = ddr_in32(&ddr->debug[28]);
|
||||
tmp &= U(0xff0fff00);
|
||||
tmp |= ddr_freq <= 1333U ? U(0x0080006a) :
|
||||
(ddr_freq <= 1600U ? U(0x0070006f) :
|
||||
(ddr_freq <= 1867U ? U(0x00700076) : U(0x0060007b)));
|
||||
if (regs->debug[28] != 0) {
|
||||
tmp &= ~0xff;
|
||||
tmp |= regs->debug[28] & 0xff;
|
||||
} else {
|
||||
WARN("Warning: Optimal CPO value not set.\n");
|
||||
}
|
||||
ddr_out32(&ddr->debug[28], tmp);
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_DDR_A010165
|
||||
ddr_freq = clk / 1000000U;
|
||||
if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
|
||||
tmp = ddr_in32(&ddr->debug[28]);
|
||||
ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
|
||||
* deasserted. Clocks start when any chip select is enabled and clock
|
||||
* control register is set. Because all DDR components are connected to
|
||||
* one reset signal, this needs to be done in two steps. Step 1 is to
|
||||
* get the clocks started. Step 2 resumes after reset signal is
|
||||
* deasserted.
|
||||
*/
|
||||
if (twopass == 1) {
|
||||
udelay(200);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* As per new sequence flow shall be write CSn_CONFIG registers needs to
|
||||
* be set after all the other DDR controller registers are set, then poll
|
||||
* for PHY_INIT_CMPLT = 1 , then wait at least 100us (micro seconds),
|
||||
* then set the MEM_EN = 1
|
||||
*/
|
||||
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
||||
if (mod_bnds != 0U && i == 0U) {
|
||||
ddr_out32(&ddr->csn_cfg[i],
|
||||
(regs->cs[i].config & ~CTLR_INTLV_MASK));
|
||||
} else {
|
||||
ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config);
|
||||
}
|
||||
}
|
||||
|
||||
after_reset:
|
||||
/* Set, but do not enable the memory */
|
||||
temp_sdram_cfg = regs->sdram_cfg[0];
|
||||
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
|
||||
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
|
||||
|
||||
if (get_ddrc_version(ddr) < U(0x50500)) {
|
||||
/*
|
||||
* 500 painful micro-seconds must elapse between
|
||||
* the DDR clock setup and the DDR config enable.
|
||||
* DDR2 need 200 us, and DDR3 need 500 us from spec,
|
||||
* we choose the max, that is 500 us for all of case.
|
||||
*/
|
||||
udelay(500);
|
||||
/* applied memory barrier */
|
||||
mb();
|
||||
isb();
|
||||
} else {
|
||||
/* wait for PHY complete */
|
||||
timeout = 40;
|
||||
while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) != 0) &&
|
||||
(timeout > 0)) {
|
||||
udelay(500);
|
||||
timeout--;
|
||||
}
|
||||
if (timeout <= 0) {
|
||||
printf("PHY handshake timeout, ddr_dsr2 = %x\n",
|
||||
ddr_in32(&ddr->ddr_dsr2));
|
||||
} else {
|
||||
debug("PHY handshake completed, timer remains %d\n",
|
||||
timeout);
|
||||
}
|
||||
}
|
||||
|
||||
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
||||
/* Let the controller go */
|
||||
udelay(100);
|
||||
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
|
||||
|
||||
/* applied memory barrier */
|
||||
mb();
|
||||
isb();
|
||||
|
||||
total_mem_per_ctrl = 0;
|
||||
for (i = 0; i < DDRC_NUM_CS; i++) {
|
||||
if ((regs->cs[i].config & 0x80000000) == 0) {
|
||||
continue;
|
||||
}
|
||||
total_mem_per_ctrl += 1 << (
|
||||
((regs->cs[i].config >> 14) & 0x3) + 2 +
|
||||
((regs->cs[i].config >> 8) & 0x7) + 12 +
|
||||
((regs->cs[i].config >> 4) & 0x3) + 0 +
|
||||
((regs->cs[i].config >> 0) & 0x7) + 8 +
|
||||
((regs->sdram_cfg[2] >> 4) & 0x3) +
|
||||
3 - ((regs->sdram_cfg[0] >> 19) & 0x3) -
|
||||
26); /* minus 26 (count of 64M) */
|
||||
}
|
||||
total_mem_per_ctrl_adj = total_mem_per_ctrl;
|
||||
/*
|
||||
* total memory / bus width = transactions needed
|
||||
* transactions needed / data rate = seconds
|
||||
* to add plenty of buffer, double the time
|
||||
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
|
||||
* Let's wait for 800ms
|
||||
*/
|
||||
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
|
||||
>> SDRAM_CFG_DBW_SHIFT);
|
||||
timeout = ((total_mem_per_ctrl_adj << (6 - bus_width)) * 100 /
|
||||
(clk >> 20)) << 2;
|
||||
total_mem_per_ctrl_adj >>= 4; /* shift down to gb size */
|
||||
if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) {
|
||||
debug("total size %d GB\n", total_mem_per_ctrl_adj);
|
||||
debug("Need to wait up to %d ms\n", timeout * 10);
|
||||
|
||||
do {
|
||||
mdelay(10);
|
||||
} while (timeout-- > 0 &&
|
||||
((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0);
|
||||
|
||||
if (timeout <= 0) {
|
||||
if (ddr_in32(&ddr->debug[1]) & 0x3d00) {
|
||||
ERROR("Found training error(s): 0x%x\n",
|
||||
ddr_in32(&ddr->debug[1]));
|
||||
}
|
||||
ERROR("Error: Waiting for D_INIT timeout.\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
if (mod_bnds != 0U) {
|
||||
debug("Restore original bnds\n");
|
||||
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
||||
ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
|
||||
}
|
||||
ddr_out32(&ddr->csn_cfg[0], regs->cs[0].config);
|
||||
#ifdef CONFIG_DDR_ADDR_DEC
|
||||
if ((regs->dec[9] & U(0x1)) != 0U) {
|
||||
debug("Restore address decoding\n");
|
||||
ddr_out32(&ddr->dec[9], regs->dec[9]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef ERRATA_DDR_A009803
|
||||
/* Part 2 of 2 */
|
||||
if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
|
||||
timeout = 400;
|
||||
do {
|
||||
mdelay(1);
|
||||
} while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
|
||||
|
||||
if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
|
||||
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
||||
if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0) {
|
||||
continue;
|
||||
}
|
||||
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
|
||||
MD_CNTL_MD_EN |
|
||||
MD_CNTL_CS_SEL(i) |
|
||||
0x070000ed,
|
||||
MD_CNTL_MD_EN);
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
ddr_out32(&ddr->err_disable,
|
||||
regs->err_disable & ~DDR_ERR_DISABLE_APED);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_DDR_A009663
|
||||
ddr_out32(&ddr->sdram_interval, regs->interval);
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_DDR_A009942
|
||||
timeout = 400;
|
||||
do {
|
||||
mdelay(1);
|
||||
} while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
|
||||
tmp = (regs->sdram_cfg[0] >> 19) & 0x3;
|
||||
check = (tmp == DDR_DBUS_64) ? 4 : ((tmp == DDR_DBUS_32) ? 2 : 1);
|
||||
for (i = 0; i < check; i++) {
|
||||
tmp = ddr_in32(&ddr->debug[9 + i]);
|
||||
debug("Reading debug[%d] as 0x%x\n", i + 9, tmp);
|
||||
cpo_min = min(cpo_min,
|
||||
min((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
|
||||
cpo_max = max(cpo_max,
|
||||
max((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
|
||||
}
|
||||
if ((regs->sdram_cfg[0] & SDRAM_CFG_ECC_EN) != 0) {
|
||||
tmp = ddr_in32(&ddr->debug[13]);
|
||||
cpo_min = min(cpo_min, (tmp >> 24) & 0xff);
|
||||
cpo_max = max(cpo_max, (tmp >> 24) & 0xff);
|
||||
}
|
||||
debug("cpo_min 0x%x\n", cpo_min);
|
||||
debug("cpo_max 0x%x\n", cpo_max);
|
||||
tmp = ddr_in32(&ddr->debug[28]);
|
||||
debug("debug[28] 0x%x\n", tmp);
|
||||
if ((cpo_min + 0x3B) < (tmp & 0xff)) {
|
||||
WARN("Warning: A009942 requires setting cpo_sample to 0x%x\n",
|
||||
(cpo_min + cpo_max) / 2 + 0x27);
|
||||
} else {
|
||||
debug("Optimal cpo_sample 0x%x\n",
|
||||
(cpo_min + cpo_max) / 2 + 0x27);
|
||||
}
|
||||
#endif
|
||||
if (run_bist() != 0) {
|
||||
if ((ddr_in32(&ddr->debug[1]) &
|
||||
((get_ddrc_version(ddr) == 0x50500) ? 0x3c00 : 0x3d00)) != 0) {
|
||||
ERROR("Found training error(s): 0x%x\n",
|
||||
ddr_in32(&ddr->debug[1]));
|
||||
return -EIO;
|
||||
}
|
||||
INFO("Running built-in self test ...\n");
|
||||
/* give it 10x time to cover whole memory */
|
||||
timeout = ((total_mem_per_ctrl << (6 - bus_width)) *
|
||||
100 / (clk >> 20)) * 10;
|
||||
INFO("\tWait up to %d ms\n", timeout * 10);
|
||||
ret = bist(ddr, timeout);
|
||||
}
|
||||
dump_ddrc((void *)ddr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,399 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <dimm.h>
|
||||
#include <i2c.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
int read_spd(unsigned char chip, void *buf, int len)
|
||||
{
|
||||
unsigned char dummy = 0U;
|
||||
int ret;
|
||||
|
||||
if (len < 256) {
|
||||
ERROR("Invalid SPD length\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
|
||||
ret = i2c_read(chip, 0, 1, buf, 256);
|
||||
if (ret == 0) {
|
||||
i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
|
||||
ret = i2c_read(chip, 0, 1, buf + 256, min(256, len - 256));
|
||||
}
|
||||
if (ret != 0) {
|
||||
zeromem(buf, len);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int crc16(unsigned char *ptr, int count)
|
||||
{
|
||||
int i;
|
||||
int crc = 0;
|
||||
|
||||
while (--count >= 0) {
|
||||
crc = crc ^ (int)*ptr++ << 8;
|
||||
for (i = 0; i < 8; ++i) {
|
||||
if ((crc & 0x8000) != 0) {
|
||||
crc = crc << 1 ^ 0x1021;
|
||||
} else {
|
||||
crc = crc << 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return crc & 0xffff;
|
||||
}
|
||||
|
||||
static int ddr4_spd_check(const struct ddr4_spd *spd)
|
||||
{
|
||||
void *p = (void *)spd;
|
||||
int csum16;
|
||||
int len;
|
||||
char crc_lsb; /* byte 126 */
|
||||
char crc_msb; /* byte 127 */
|
||||
|
||||
len = 126;
|
||||
csum16 = crc16(p, len);
|
||||
|
||||
crc_lsb = (char) (csum16 & 0xff);
|
||||
crc_msb = (char) (csum16 >> 8);
|
||||
|
||||
if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) {
|
||||
ERROR("SPD CRC = 0x%x%x, computed CRC = 0x%x%x\n",
|
||||
spd->crc[1], spd->crc[0], crc_msb, crc_lsb);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
p = (void *)spd + 128;
|
||||
len = 126;
|
||||
csum16 = crc16(p, len);
|
||||
|
||||
crc_lsb = (char) (csum16 & 0xff);
|
||||
crc_msb = (char) (csum16 >> 8);
|
||||
|
||||
if (spd->mod_section.uc[126] != crc_lsb ||
|
||||
spd->mod_section.uc[127] != crc_msb) {
|
||||
ERROR("SPD CRC = 0x%x%x, computed CRC = 0x%x%x\n",
|
||||
spd->mod_section.uc[127], spd->mod_section.uc[126],
|
||||
crc_msb, crc_lsb);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long long
|
||||
compute_ranksize(const struct ddr4_spd *spd)
|
||||
{
|
||||
unsigned long long bsize;
|
||||
|
||||
int nbit_sdram_cap_bsize = 0;
|
||||
int nbit_primary_bus_width = 0;
|
||||
int nbit_sdram_width = 0;
|
||||
int die_count = 0;
|
||||
bool package_3ds;
|
||||
|
||||
if ((spd->density_banks & 0xf) <= 7) {
|
||||
nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
|
||||
}
|
||||
if ((spd->bus_width & 0x7) < 4) {
|
||||
nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
|
||||
}
|
||||
if ((spd->organization & 0x7) < 4) {
|
||||
nbit_sdram_width = (spd->organization & 0x7) + 2;
|
||||
}
|
||||
package_3ds = (spd->package_type & 0x3) == 0x2;
|
||||
if (package_3ds) {
|
||||
die_count = (spd->package_type >> 4) & 0x7;
|
||||
}
|
||||
|
||||
bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
|
||||
nbit_primary_bus_width - nbit_sdram_width +
|
||||
die_count);
|
||||
|
||||
return bsize;
|
||||
}
|
||||
|
||||
int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
static const unsigned char udimm_rc_e_dq[18] = {
|
||||
0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
|
||||
0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
|
||||
};
|
||||
int spd_error = 0;
|
||||
unsigned char *ptr;
|
||||
unsigned char val;
|
||||
|
||||
if (spd->mem_type != SPD_MEMTYPE_DDR4) {
|
||||
ERROR("Not a DDR4 DIMM.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = ddr4_spd_check(spd);
|
||||
if (ret != 0) {
|
||||
ERROR("DIMM SPD checksum mismatch\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* The part name in ASCII in the SPD EEPROM is not null terminated.
|
||||
* Guarantee null termination here by presetting all bytes to 0
|
||||
* and copying the part name in ASCII from the SPD onto it
|
||||
*/
|
||||
if ((spd->info_size_crc & 0xF) > 2) {
|
||||
memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
|
||||
}
|
||||
|
||||
/* DIMM organization parameters */
|
||||
pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
|
||||
debug("n_ranks %d\n", pdimm->n_ranks);
|
||||
pdimm->rank_density = compute_ranksize(spd);
|
||||
if (pdimm->rank_density == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
debug("rank_density 0x%llx\n", pdimm->rank_density);
|
||||
pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
|
||||
debug("capacity 0x%llx\n", pdimm->capacity);
|
||||
pdimm->die_density = spd->density_banks & 0xf;
|
||||
debug("die density 0x%x\n", pdimm->die_density);
|
||||
pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
|
||||
debug("primary_sdram_width %d\n", pdimm->primary_sdram_width);
|
||||
if (((spd->bus_width >> 3) & 0x3) != 0) {
|
||||
pdimm->ec_sdram_width = 8;
|
||||
} else {
|
||||
pdimm->ec_sdram_width = 0;
|
||||
}
|
||||
debug("ec_sdram_width %d\n", pdimm->ec_sdram_width);
|
||||
pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
|
||||
debug("device_width %d\n", pdimm->device_width);
|
||||
pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
|
||||
(spd->package_type >> 4) & 0x7 : 0;
|
||||
debug("package_3ds %d\n", pdimm->package_3ds);
|
||||
|
||||
switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
|
||||
case DDR4_SPD_RDIMM:
|
||||
case DDR4_SPD_MINI_RDIMM:
|
||||
case DDR4_SPD_72B_SO_RDIMM:
|
||||
pdimm->rdimm = 1;
|
||||
pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x8f;
|
||||
if ((spd->mod_section.registered.reg_map & 0x1) != 0) {
|
||||
pdimm->mirrored_dimm = 1;
|
||||
}
|
||||
val = spd->mod_section.registered.ca_stren;
|
||||
pdimm->rcw[3] = val >> 4;
|
||||
pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
|
||||
val = spd->mod_section.registered.clk_stren;
|
||||
pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
|
||||
pdimm->rcw[6] = 0xf;
|
||||
/* A17 used for 16Gb+, C[2:0] used for 3DS */
|
||||
pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
|
||||
(pdimm->package_3ds > 0x3 ? 0x0 :
|
||||
(pdimm->package_3ds > 0x1 ? 0x1 :
|
||||
(pdimm->package_3ds > 0 ? 0x2 : 0x3)));
|
||||
if (pdimm->package_3ds != 0 || pdimm->n_ranks != 4) {
|
||||
pdimm->rcw[13] = 0x4;
|
||||
} else {
|
||||
pdimm->rcw[13] = 0x5;
|
||||
}
|
||||
pdimm->rcw[13] |= pdimm->mirrored_dimm ? 0x8 : 0;
|
||||
break;
|
||||
|
||||
case DDR4_SPD_UDIMM:
|
||||
case DDR4_SPD_SO_DIMM:
|
||||
case DDR4_SPD_MINI_UDIMM:
|
||||
case DDR4_SPD_72B_SO_UDIMM:
|
||||
case DDR4_SPD_16B_SO_DIMM:
|
||||
case DDR4_SPD_32B_SO_DIMM:
|
||||
pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x8f;
|
||||
if ((spd->mod_section.unbuffered.addr_mapping & 0x1) != 0) {
|
||||
pdimm->mirrored_dimm = 1;
|
||||
}
|
||||
if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
|
||||
(spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
|
||||
/* Fix SPD error found on DIMMs with raw card E0 */
|
||||
for (i = 0; i < 18; i++) {
|
||||
if (spd->mapping[i] == udimm_rc_e_dq[i]) {
|
||||
continue;
|
||||
}
|
||||
spd_error = 1;
|
||||
ptr = (unsigned char *)&spd->mapping[i];
|
||||
*ptr = udimm_rc_e_dq[i];
|
||||
}
|
||||
if (spd_error != 0) {
|
||||
INFO("SPD DQ mapping error fixed\n");
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("Unknown module_type 0x%x\n", spd->module_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
debug("rdimm %d\n", pdimm->rdimm);
|
||||
debug("mirrored_dimm %d\n", pdimm->mirrored_dimm);
|
||||
debug("rc 0x%x\n", pdimm->rc);
|
||||
|
||||
/* SDRAM device parameters */
|
||||
pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
|
||||
debug("n_row_addr %d\n", pdimm->n_row_addr);
|
||||
pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
|
||||
debug("n_col_addr %d\n", pdimm->n_col_addr);
|
||||
pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
|
||||
debug("bank_addr_bits %d\n", pdimm->bank_addr_bits);
|
||||
pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
|
||||
debug("bank_group_bits %d\n", pdimm->bank_group_bits);
|
||||
|
||||
if (pdimm->ec_sdram_width != 0) {
|
||||
pdimm->edc_config = 0x02;
|
||||
} else {
|
||||
pdimm->edc_config = 0x00;
|
||||
}
|
||||
debug("edc_config %d\n", pdimm->edc_config);
|
||||
|
||||
/* DDR4 spec has BL8 -bit3, BC4 -bit2 */
|
||||
pdimm->burst_lengths_bitmask = 0x0c;
|
||||
debug("burst_lengths_bitmask 0x%x\n", pdimm->burst_lengths_bitmask);
|
||||
|
||||
/* MTB - medium timebase
|
||||
* The MTB in the SPD spec is 125ps,
|
||||
*
|
||||
* FTB - fine timebase
|
||||
* use 1/10th of ps as our unit to avoid floating point
|
||||
* eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
|
||||
*/
|
||||
if ((spd->timebases & 0xf) == 0x0) {
|
||||
pdimm->mtb_ps = 125;
|
||||
pdimm->ftb_10th_ps = 10;
|
||||
|
||||
} else {
|
||||
ERROR("Unknown Timebases\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* sdram minimum cycle time */
|
||||
pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
|
||||
debug("tckmin_x_ps %d\n", pdimm->tckmin_x_ps);
|
||||
|
||||
/* sdram max cycle time */
|
||||
pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
|
||||
debug("tckmax_ps %d\n", pdimm->tckmax_ps);
|
||||
|
||||
/*
|
||||
* CAS latency supported
|
||||
* bit0 - CL7
|
||||
* bit4 - CL11
|
||||
* bit8 - CL15
|
||||
* bit12- CL19
|
||||
* bit16- CL23
|
||||
*/
|
||||
pdimm->caslat_x = (spd->caslat_b1 << 7) |
|
||||
(spd->caslat_b2 << 15) |
|
||||
(spd->caslat_b3 << 23);
|
||||
debug("caslat_x 0x%x\n", pdimm->caslat_x);
|
||||
|
||||
if (spd->caslat_b4 != 0) {
|
||||
WARN("Unhandled caslat_b4 value\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* min CAS latency time
|
||||
*/
|
||||
pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
|
||||
debug("taa_ps %d\n", pdimm->taa_ps);
|
||||
|
||||
/*
|
||||
* min RAS to CAS delay time
|
||||
*/
|
||||
pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
|
||||
debug("trcd_ps %d\n", pdimm->trcd_ps);
|
||||
|
||||
/*
|
||||
* Min Row Precharge Delay Time
|
||||
*/
|
||||
pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
|
||||
debug("trp_ps %d\n", pdimm->trp_ps);
|
||||
|
||||
/* min active to precharge delay time */
|
||||
pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
|
||||
spd->tras_min_lsb) * pdimm->mtb_ps;
|
||||
debug("tras_ps %d\n", pdimm->tras_ps);
|
||||
|
||||
/* min active to actice/refresh delay time */
|
||||
pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
|
||||
spd->trc_min_lsb), spd->fine_trc_min);
|
||||
debug("trc_ps %d\n", pdimm->trc_ps);
|
||||
/* Min Refresh Recovery Delay Time */
|
||||
pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
|
||||
pdimm->mtb_ps;
|
||||
debug("trfc1_ps %d\n", pdimm->trfc1_ps);
|
||||
pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
|
||||
pdimm->mtb_ps;
|
||||
debug("trfc2_ps %d\n", pdimm->trfc2_ps);
|
||||
pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
|
||||
pdimm->mtb_ps;
|
||||
debug("trfc4_ps %d\n", pdimm->trfc4_ps);
|
||||
/* min four active window delay time */
|
||||
pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
|
||||
pdimm->mtb_ps;
|
||||
debug("tfaw_ps %d\n", pdimm->tfaw_ps);
|
||||
|
||||
/* min row active to row active delay time, different bank group */
|
||||
pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
|
||||
debug("trrds_ps %d\n", pdimm->trrds_ps);
|
||||
/* min row active to row active delay time, same bank group */
|
||||
pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
|
||||
debug("trrdl_ps %d\n", pdimm->trrdl_ps);
|
||||
/* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
|
||||
pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
|
||||
debug("tccdl_ps %d\n", pdimm->tccdl_ps);
|
||||
if (pdimm->package_3ds != 0) {
|
||||
if (pdimm->die_density > 5) {
|
||||
debug("Unsupported logical rank density 0x%x\n",
|
||||
pdimm->die_density);
|
||||
return -EINVAL;
|
||||
}
|
||||
pdimm->trfc_slr_ps = (pdimm->die_density <= 4) ?
|
||||
260000 : 350000;
|
||||
}
|
||||
debug("trfc_slr_ps %d\n", pdimm->trfc_slr_ps);
|
||||
|
||||
/* 15ns for all speed bins */
|
||||
pdimm->twr_ps = 15000;
|
||||
debug("twr_ps %d\n", pdimm->twr_ps);
|
||||
|
||||
/*
|
||||
* Average periodic refresh interval
|
||||
* tREFI = 7.8 us at normal temperature range
|
||||
*/
|
||||
pdimm->refresh_rate_ps = 7800000;
|
||||
debug("refresh_rate_ps %d\n", pdimm->refresh_rate_ps);
|
||||
|
||||
for (i = 0; i < 18; i++) {
|
||||
pdimm->dq_mapping[i] = spd->mapping[i];
|
||||
debug("dq_mapping 0x%x\n", pdimm->dq_mapping[i]);
|
||||
}
|
||||
|
||||
pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
|
||||
debug("dq_mapping_ors %d\n", pdimm->dq_mapping_ors);
|
||||
|
||||
return 0;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <immap.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#define UL_5POW12 244140625UL
|
||||
#define ULL_2E12 2000000000000ULL
|
||||
#define UL_2POW13 (1UL << 13)
|
||||
#define ULL_8FS 0xFFFFFFFFULL
|
||||
|
||||
#define do_div(n, base) ({ \
|
||||
unsigned int __base = (base); \
|
||||
unsigned int __rem; \
|
||||
__rem = ((unsigned long long)(n)) % __base; \
|
||||
(n) = ((unsigned long long)(n)) / __base; \
|
||||
__rem; \
|
||||
})
|
||||
|
||||
#define CCN_HN_F_SAM_NODEID_MASK 0x7f
|
||||
#ifdef NXP_HAS_CCN504
|
||||
#define CCN_HN_F_SAM_NODEID_DDR0 0x4
|
||||
#define CCN_HN_F_SAM_NODEID_DDR1 0xe
|
||||
#elif defined(NXP_HAS_CCN508)
|
||||
#define CCN_HN_F_SAM_NODEID_DDR0 0x8
|
||||
#define CCN_HN_F_SAM_NODEID_DDR1 0x18
|
||||
#endif
|
||||
|
||||
unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num)
|
||||
{
|
||||
if (sys->freq_ddr_pll0 == 0) {
|
||||
get_clocks(sys);
|
||||
}
|
||||
|
||||
switch (ctrl_num) {
|
||||
case 0:
|
||||
return sys->freq_ddr_pll0;
|
||||
case 1:
|
||||
return sys->freq_ddr_pll0;
|
||||
case 2:
|
||||
return sys->freq_ddr_pll1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int get_memory_clk_ps(const unsigned long data_rate)
|
||||
{
|
||||
unsigned int result;
|
||||
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
|
||||
unsigned long long rem, mclk_ps = ULL_2E12;
|
||||
|
||||
/* Now perform the big divide, the result fits in 32-bits */
|
||||
rem = do_div(mclk_ps, data_rate);
|
||||
result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos)
|
||||
{
|
||||
unsigned long long clks, clks_rem;
|
||||
|
||||
/* Short circuit for zero picos */
|
||||
if ((picos == 0U) || (data_rate == 0UL)) {
|
||||
return 0U;
|
||||
}
|
||||
|
||||
/* First multiply the time by the data rate (32x32 => 64) */
|
||||
clks = picos * (unsigned long long)data_rate;
|
||||
/*
|
||||
* Now divide by 5^12 and track the 32-bit remainder, then divide
|
||||
* by 2*(2^12) using shifts (and updating the remainder).
|
||||
*/
|
||||
clks_rem = do_div(clks, UL_5POW12);
|
||||
clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
|
||||
clks >>= 13U;
|
||||
|
||||
/* If we had a remainder greater than the 1ps error, then round up */
|
||||
if (clks_rem > data_rate) {
|
||||
clks++;
|
||||
}
|
||||
|
||||
/* Clamp to the maximum representable value */
|
||||
if (clks > ULL_8FS) {
|
||||
clks = ULL_8FS;
|
||||
}
|
||||
return (unsigned int) clks;
|
||||
}
|
||||
|
||||
/* valid_spd_mask has been checked by parse_spd */
|
||||
int disable_unused_ddrc(struct ddr_info *priv,
|
||||
int valid_spd_mask, uintptr_t nxp_ccn_hn_f0_addr)
|
||||
{
|
||||
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
|
||||
void *hnf_sam_ctrl = (void *)(nxp_ccn_hn_f0_addr + CCN_HN_F_SAM_CTL);
|
||||
uint32_t val, nodeid;
|
||||
#ifdef NXP_HAS_CCN504
|
||||
uint32_t num_hnf_nodes = 4U;
|
||||
#else
|
||||
uint32_t num_hnf_nodes = 8U;
|
||||
#endif
|
||||
int disable_ddrc = 0;
|
||||
int i;
|
||||
|
||||
if (priv->num_ctlrs < 2) {
|
||||
debug("%s: nothing to do.\n", __func__);
|
||||
}
|
||||
|
||||
switch (priv->dimm_on_ctlr) {
|
||||
case 1:
|
||||
disable_ddrc = ((valid_spd_mask &0x2) == 0) ? 2 : 0;
|
||||
disable_ddrc = ((valid_spd_mask &0x1) == 0) ? 1 : disable_ddrc;
|
||||
break;
|
||||
case 2:
|
||||
disable_ddrc = ((valid_spd_mask &0x4) == 0) ? 2 : 0;
|
||||
disable_ddrc = ((valid_spd_mask &0x1) == 0) ? 1 : disable_ddrc;
|
||||
break;
|
||||
default:
|
||||
ERROR("Invalid number of DIMMs %d\n", priv->dimm_on_ctlr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (disable_ddrc != 0) {
|
||||
debug("valid_spd_mask = 0x%x\n", valid_spd_mask);
|
||||
}
|
||||
|
||||
switch (disable_ddrc) {
|
||||
case 1:
|
||||
priv->num_ctlrs = 1;
|
||||
priv->spd_addr = &priv->spd_addr[priv->dimm_on_ctlr];
|
||||
priv->ddr[0] = priv->ddr[1];
|
||||
priv->ddr[1] = NULL;
|
||||
priv->phy[0] = priv->phy[0];
|
||||
priv->phy[1] = NULL;
|
||||
debug("Disable first DDR controller\n");
|
||||
break;
|
||||
case 2:
|
||||
priv->num_ctlrs = 1;
|
||||
priv->ddr[1] = NULL;
|
||||
priv->phy[1] = NULL;
|
||||
debug("Disable second DDR controller\n");
|
||||
/* fallthrough */
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
ERROR("Program error.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (disable_ddrc == 0) {
|
||||
debug("Both controllers in use.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_hnf_nodes; i++) {
|
||||
val = mmio_read_64((uintptr_t)hnf_sam_ctrl);
|
||||
nodeid = disable_ddrc == 1 ? CCN_HN_F_SAM_NODEID_DDR1 :
|
||||
(disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 :
|
||||
(i < 4 ? CCN_HN_F_SAM_NODEID_DDR0
|
||||
: CCN_HN_F_SAM_NODEID_DDR1));
|
||||
if (nodeid != (val & CCN_HN_F_SAM_NODEID_MASK)) {
|
||||
debug("Setting HN-F node %d\n", i);
|
||||
debug("nodeid = 0x%x\n", nodeid);
|
||||
val &= ~CCN_HN_F_SAM_NODEID_MASK;
|
||||
val |= nodeid;
|
||||
mmio_write_64((uintptr_t)hnf_sam_ctrl, val);
|
||||
}
|
||||
hnf_sam_ctrl += CCN_HN_F_REGION_SIZE;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int get_ddrc_version(const struct ccsr_ddr *ddr)
|
||||
{
|
||||
unsigned int ver;
|
||||
|
||||
ver = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8U;
|
||||
ver |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8U;
|
||||
|
||||
return ver;
|
||||
}
|
||||
|
||||
void print_ddr_info(struct ccsr_ddr *ddr)
|
||||
{
|
||||
unsigned int cs0_config = ddr_in32(&ddr->csn_cfg[0]);
|
||||
unsigned int sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
||||
int cas_lat;
|
||||
|
||||
if ((sdram_cfg & SDRAM_CFG_MEM_EN) == 0U) {
|
||||
printf(" (DDR not enabled)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("DDR");
|
||||
switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
|
||||
SDRAM_CFG_SDRAM_TYPE_SHIFT) {
|
||||
case SDRAM_TYPE_DDR4:
|
||||
printf("4");
|
||||
break;
|
||||
default:
|
||||
printf("?");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (sdram_cfg & SDRAM_CFG_DBW_MASK) {
|
||||
case SDRAM_CFG_32_BW:
|
||||
printf(", 32-bit");
|
||||
break;
|
||||
case SDRAM_CFG_16_BW:
|
||||
printf(", 16-bit");
|
||||
break;
|
||||
case SDRAM_CFG_8_BW:
|
||||
printf(", 8-bit");
|
||||
break;
|
||||
default:
|
||||
printf(", 64-bit");
|
||||
break;
|
||||
}
|
||||
|
||||
/* Calculate CAS latency based on timing cfg values */
|
||||
cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
|
||||
cas_lat += 2; /* for DDRC newer than 4.4 */
|
||||
cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
|
||||
printf(", CL=%d", cas_lat >> 1);
|
||||
if ((cas_lat & 0x1) != 0) {
|
||||
printf(".5");
|
||||
}
|
||||
|
||||
if ((sdram_cfg & SDRAM_CFG_ECC_EN) != 0) {
|
||||
printf(", ECC on");
|
||||
} else {
|
||||
printf(", ECC off");
|
||||
}
|
||||
|
||||
if ((cs0_config & 0x20000000) != 0) {
|
||||
printf(", ");
|
||||
switch ((cs0_config >> 24) & 0xf) {
|
||||
case DDR_256B_INTLV:
|
||||
printf("256B");
|
||||
break;
|
||||
default:
|
||||
printf("invalid");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (((sdram_cfg >> 8) & 0x7f) != 0) {
|
||||
printf(", ");
|
||||
switch (sdram_cfg >> 8 & 0x7f) {
|
||||
case DDR_BA_INTLV_CS0123:
|
||||
printf("CS0+CS1+CS2+CS3");
|
||||
break;
|
||||
case DDR_BA_INTLV_CS01:
|
||||
printf("CS0+CS1");
|
||||
break;
|
||||
default:
|
||||
printf("invalid");
|
||||
break;
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
|
||||
static void cal_ddr_sdram_clk_cntl(struct ddr_cfg_regs *regs,
|
||||
const struct memctl_opt *popts)
|
||||
{
|
||||
const unsigned int clk_adj = popts->clk_adj;
|
||||
const unsigned int ss_en = 0U;
|
||||
|
||||
regs->clk_cntl = ((ss_en & U(0x1)) << 31U) |
|
||||
((clk_adj & U(0x1F)) << 22U);
|
||||
debug("clk_cntl = 0x%x\n", regs->clk_cntl);
|
||||
}
|
||||
|
||||
static void cal_ddr_cdr(struct ddr_cfg_regs *regs,
|
||||
const struct memctl_opt *popts)
|
||||
{
|
||||
regs->cdr[0] = popts->ddr_cdr1;
|
||||
regs->cdr[1] = popts->ddr_cdr2;
|
||||
debug("cdr[0] = 0x%x\n", regs->cdr[0]);
|
||||
debug("cdr[1] = 0x%x\n", regs->cdr[1]);
|
||||
}
|
||||
|
||||
static void cal_ddr_wrlvl_cntl(struct ddr_cfg_regs *regs,
|
||||
const struct memctl_opt *popts)
|
||||
{
|
||||
const unsigned int wrlvl_en = 1U; /* enabled */
|
||||
const unsigned int wrlvl_mrd = U(0x6); /* > 40nCK */
|
||||
const unsigned int wrlvl_odten = U(0x7); /* 128 */
|
||||
const unsigned int wrlvl_dqsen = U(0x5); /* > 25nCK */
|
||||
const unsigned int wrlvl_wlr = U(0x6); /* > tWLO + 6 */
|
||||
const unsigned int wrlvl_smpl = popts->wrlvl_override ?
|
||||
popts->wrlvl_sample : U(0xf);
|
||||
const unsigned int wrlvl_start = popts->wrlvl_start;
|
||||
|
||||
regs->wrlvl_cntl[0] = ((wrlvl_en & U(0x1)) << 31U) |
|
||||
((wrlvl_mrd & U(0x7)) << 24U) |
|
||||
((wrlvl_odten & U(0x7)) << 20U) |
|
||||
((wrlvl_dqsen & U(0x7)) << 16U) |
|
||||
((wrlvl_smpl & U(0xf)) << 12U) |
|
||||
((wrlvl_wlr & U(0x7)) << 8U) |
|
||||
((wrlvl_start & U(0x1F)) << 0U);
|
||||
regs->wrlvl_cntl[1] = popts->wrlvl_ctl_2;
|
||||
regs->wrlvl_cntl[2] = popts->wrlvl_ctl_3;
|
||||
debug("wrlvl_cntl[0] = 0x%x\n", regs->wrlvl_cntl[0]);
|
||||
debug("wrlvl_cntl[1] = 0x%x\n", regs->wrlvl_cntl[1]);
|
||||
debug("wrlvl_cntl[2] = 0x%x\n", regs->wrlvl_cntl[2]);
|
||||
|
||||
}
|
||||
|
||||
static void cal_ddr_dbg(struct ddr_cfg_regs *regs,
|
||||
const struct memctl_opt *popts)
|
||||
{
|
||||
if (popts->cswl_override != 0) {
|
||||
regs->debug[18] = popts->cswl_override;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR_EMU
|
||||
/* disable DDR training for emulator */
|
||||
regs->debug[2] = U(0x00000400);
|
||||
regs->debug[4] = U(0xff800800);
|
||||
regs->debug[5] = U(0x08000800);
|
||||
regs->debug[6] = U(0x08000800);
|
||||
regs->debug[7] = U(0x08000800);
|
||||
regs->debug[8] = U(0x08000800);
|
||||
#endif
|
||||
if (popts->cpo_sample != 0U) {
|
||||
regs->debug[28] = popts->cpo_sample;
|
||||
debug("debug[28] = 0x%x\n", regs->debug[28]);
|
||||
}
|
||||
}
|
||||
|
||||
int compute_ddr_phy(struct ddr_info *priv)
|
||||
{
|
||||
const struct memctl_opt *popts = &priv->opt;
|
||||
struct ddr_cfg_regs *regs = &priv->ddr_reg;
|
||||
|
||||
cal_ddr_sdram_clk_cntl(regs, popts);
|
||||
cal_ddr_cdr(regs, popts);
|
||||
cal_ddr_wrlvl_cntl(regs, popts);
|
||||
cal_ddr_dbg(regs, popts);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CSR_H
|
||||
#define CSR_H
|
||||
|
||||
#define t_anib 0
|
||||
#define t_dbyte 0x10000
|
||||
#define t_master 0x20000
|
||||
#define t_acsm 0x40000
|
||||
#define t_initeng 0x90000
|
||||
#define t_drtub 0xc0000
|
||||
#define t_apbonly 0xd0000
|
||||
#define csr_dbyte_misc_mode_addr 0x00
|
||||
#define csr_micro_cont_mux_sel_addr 0x00
|
||||
#define csr_uct_shadow_regs 0x04
|
||||
#define csr_cal_uclk_info_addr 0x08
|
||||
#define csr_seq0bdly0_addr 0x0b
|
||||
#define csr_seq0bdly1_addr 0x0c
|
||||
#define csr_seq0bdly2_addr 0x0d
|
||||
#define csr_seq0bdly3_addr 0x0e
|
||||
#define csr_seq0bdisable_flag0_addr 0x0c
|
||||
#define csr_seq0bdisable_flag1_addr 0x0d
|
||||
#define csr_seq0bdisable_flag2_addr 0x0e
|
||||
#define csr_seq0bdisable_flag3_addr 0x0f
|
||||
#define csr_seq0bdisable_flag4_addr 0x10
|
||||
#define csr_seq0bdisable_flag5_addr 0x11
|
||||
#define csr_seq0bdisable_flag6_addr 0x12
|
||||
#define csr_seq0bdisable_flag7_addr 0x13
|
||||
#define csr_dfi_mode_addr 0x18
|
||||
#define csr_tristate_mode_ca_addr 0x19
|
||||
#define csr_dfiphyupd_addr 0x21
|
||||
#define csr_dqs_preamble_control_addr 0x24
|
||||
#define csr_master_x4config_addr 0x25
|
||||
#define csr_enable_cs_multicast_addr 0x27
|
||||
#define csr_acx4_anib_dis_addr 0x2c
|
||||
#define csr_dmipin_present_addr 0x2d
|
||||
#define csr_ard_ptr_init_val_addr 0x2e
|
||||
#define csr_dct_write_prot 0x31
|
||||
#define csr_uct_write_only_shadow 0x32
|
||||
#define csr_uct_write_prot 0x33
|
||||
#define csr_uct_dat_write_only_shadow 0x34
|
||||
#define csr_dbyte_dll_mode_cntrl_addr 0x3a
|
||||
#define csr_atx_impedance_addr 0x43
|
||||
#define csr_dq_dqs_rcv_cntrl_addr 0x43
|
||||
#define csr_cal_offsets_addr 0x45
|
||||
#define csr_tx_impedance_ctrl1_addr 0x49
|
||||
#define csr_dq_dqs_rcv_cntrl1_addr 0x4a
|
||||
#define csr_tx_odt_drv_stren_addr 0x4d
|
||||
#define csr_cal_drv_str0_addr 0x50
|
||||
#define csr_atx_slew_rate_addr 0x55
|
||||
#define csr_proc_odt_time_ctl_addr 0x56
|
||||
#define csr_mem_alert_control_addr 0x5b
|
||||
#define csr_mem_alert_control2_addr 0x5c
|
||||
#define csr_tx_slew_rate_addr 0x5f
|
||||
#define csr_mem_reset_l_addr 0x60
|
||||
#define csr_dfi_camode_addr 0x75
|
||||
#define csr_dll_gain_ctl_addr 0x7c
|
||||
#define csr_dll_lockparam_addr 0x7d
|
||||
#define csr_ucclk_hclk_enables_addr 0x80
|
||||
#define csr_acsm_playback0x0_addr 0x80
|
||||
#define csr_acsm_playback1x0_addr 0x81
|
||||
#define csr_cal_rate_addr 0x88
|
||||
#define csr_cal_zap_addr 0x89
|
||||
#define csr_cal_misc2_addr 0x98
|
||||
#define csr_micro_reset_addr 0x99
|
||||
#define csr_dfi_rd_data_cs_dest_map_addr 0xb0
|
||||
#define csr_vref_in_global_addr 0xb2
|
||||
#define csr_dfi_wr_data_cs_dest_map_addr 0xb4
|
||||
#define csr_pll_pwr_dn_addr 0xc3
|
||||
#define csr_pll_ctrl2_addr 0xc5
|
||||
#define csr_pll_ctrl1_addr 0xc7
|
||||
#define csr_pll_test_mode_addr 0xca
|
||||
#define csr_pll_ctrl4_addr 0xcc
|
||||
#define csr_dfi_freq_xlat0_addr 0xf0
|
||||
#define csr_acsm_ctrl0_addr 0xf0
|
||||
#define csr_dfi_freq_ratio_addr 0xfa
|
||||
#define csr_acsm_ctrl13_addr 0xfd
|
||||
#define csr_tx_pre_drv_mode_lsb 8
|
||||
#define csr_tx_pre_n_lsb 4
|
||||
#define csr_tx_pre_p_lsb 0
|
||||
#define csr_atx_pre_drv_mode_lsb 8
|
||||
#define csr_atx_pre_n_lsb 4
|
||||
#define csr_atx_pre_p_lsb 0
|
||||
#define csr_wdqsextension_lsb 8
|
||||
#define csr_lp4sttc_pre_bridge_rx_en_lsb 7
|
||||
#define csr_lp4postamble_ext_lsb 6
|
||||
#define csr_lp4tgl_two_tck_tx_dqs_pre_lsb 5
|
||||
#define csr_position_dfe_init_lsb 2
|
||||
#define csr_two_tck_tx_dqs_pre_lsb 1
|
||||
#define csr_two_tck_rx_dqs_pre_lsb 0
|
||||
#define csr_dll_rx_preamble_mode_lsb 1
|
||||
#define csr_odtstren_n_lsb 6
|
||||
#define csr_drv_stren_fsdq_n_lsb 6
|
||||
#define csr_drv_stren_fsdq_p_lsb 0
|
||||
#define csr_adrv_stren_n_lsb 5
|
||||
#define csr_adrv_stren_p_lsb 0
|
||||
#define csr_cal_drv_str_pu50_lsb 4
|
||||
#define csr_cal_once_lsb 5
|
||||
#define csr_cal_interval_lsb 0
|
||||
#define csr_cal_run_lsb 4
|
||||
#define csr_global_vref_in_dac_lsb 3
|
||||
#define csr_gain_curr_adj_lsb 7
|
||||
#define csr_major_mode_dbyte_lsb 4
|
||||
#define csr_dfe_ctrl_lsb 2
|
||||
#define csr_ext_vref_range_lsb 1
|
||||
#define csr_sel_analog_vref_lsb 0
|
||||
#define csr_malertsync_bypass_lsb 0
|
||||
#define csr_ck_dis_val_lsb 2
|
||||
#define csr_ddr2tmode_lsb 1
|
||||
#define csr_dis_dyn_adr_tri_lsb 0
|
||||
#define csr_dbyte_disable_lsb 2
|
||||
#define csr_power_down_rcvr_lsb 0
|
||||
#define csr_power_down_rcvr_dqs_lsb 9
|
||||
#define csr_rx_pad_standby_en_lsb 10
|
||||
#define csr_rx_pad_standby_en_mask 0x400
|
||||
#define csr_x4tg_lsb 0
|
||||
#define csr_reset_to_micro_mask 0x8
|
||||
#define csr_protect_mem_reset_mask 0x2
|
||||
#define csr_stall_to_micro_mask 0x1
|
||||
#define uct_write_prot_shadow_mask 0x1
|
||||
#define csr_acsm_par_mode_mask 0x4000
|
||||
#define csr_acsm_cke_enb_lsb 0
|
||||
#define csr_dfiphyupd_threshold_lsb 8
|
||||
#define csr_dfiphyupd_threshold_msb 11
|
||||
#define csr_dfiphyupd_threshold_mask 0xf00
|
||||
#define csr_dfi_rd_destm0_lsb 0
|
||||
#define csr_dfi_rd_destm1_lsb 2
|
||||
#define csr_dfi_rd_destm2_lsb 4
|
||||
#define csr_dfi_rd_destm3_lsb 6
|
||||
#define csr_dfi_wr_destm0_lsb 0
|
||||
#define csr_dfi_wr_destm1_lsb 2
|
||||
#define csr_dfi_wr_destm2_lsb 4
|
||||
#define csr_dfi_wr_destm3_lsb 6
|
||||
#define csr_acsm_2t_mode_mask 0x40
|
||||
#define csr_cal_misc2_err_dis 13
|
||||
#define csr_cal_offset_pdc_lsb 6
|
||||
#define csr_cal_offset_pdc_msb 9
|
||||
#define csr_cal_offset_pdc_mask 0xe0
|
||||
#define csr_cal_drv_pdth_mask 0x3c0
|
||||
|
||||
|
||||
struct impedance_mapping {
|
||||
int ohm;
|
||||
int code;
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Copyright 2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# SNPS ddr phy driver files
|
||||
|
||||
DDR_PHY_C =
|
||||
DDR_PHY_H =
|
||||
|
||||
$(DDR_PHY_C): $(DDR_PHY_H) $(COMMON_HDRS) src
|
||||
@cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
|
||||
|
||||
$(DDR_PHY_H): src
|
||||
@cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
|
||||
|
||||
#------------------------------------------------
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _INPUT_H_
|
||||
#define _INPUT_H_
|
||||
|
||||
enum dram_types {
|
||||
DDR4,
|
||||
DDR3,
|
||||
LPDDR4,
|
||||
LPDDR3,
|
||||
LPDDR2,
|
||||
DDR5,
|
||||
};
|
||||
|
||||
enum dimm_types {
|
||||
UDIMM,
|
||||
SODIMM,
|
||||
RDIMM,
|
||||
LRDIMM,
|
||||
NODIMM,
|
||||
};
|
||||
|
||||
struct input_basic {
|
||||
enum dram_types dram_type;
|
||||
enum dimm_types dimm_type;
|
||||
int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4
|
||||
*/
|
||||
/* not used for protocols other than lpddr4 */
|
||||
int num_dbyte; /* number of dbytes physically instantiated */
|
||||
int num_active_dbyte_dfi0; /* number of active dbytes to be
|
||||
* controlled by dfi0
|
||||
*/
|
||||
int num_active_dbyte_dfi1; /* number of active dbytes to be
|
||||
* controlled by dfi1. Not used for
|
||||
* protocols other than lpddr3 and
|
||||
* lpddr4
|
||||
*/
|
||||
int num_anib; /* number of anibs physically instantiated */
|
||||
int num_rank_dfi0; /* number of ranks in dfi0 channel */
|
||||
int num_rank_dfi1; /* number of ranks in dfi1 channel */
|
||||
int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram
|
||||
* type
|
||||
*/
|
||||
int num_pstates;
|
||||
int frequency; /* memclk frequency in mhz -- round up */
|
||||
int pll_bypass; /* pll bypass enable */
|
||||
int dfi_freq_ratio; /* selected dfi frequency ratio */
|
||||
int dfi1exists; /* whether they phy config has dfi1 channel */
|
||||
int train2d;
|
||||
int hard_macro_ver;
|
||||
int read_dbienable;
|
||||
int dfi_mode; /* no longer used */
|
||||
};
|
||||
|
||||
struct input_advanced {
|
||||
int d4rx_preamble_length;
|
||||
int d4tx_preamble_length;
|
||||
int ext_cal_res_val; /* external pull-down resistor */
|
||||
int is2ttiming;
|
||||
int odtimpedance;
|
||||
int tx_impedance;
|
||||
int atx_impedance;
|
||||
int mem_alert_en;
|
||||
int mem_alert_puimp;
|
||||
int mem_alert_vref_level;
|
||||
int mem_alert_sync_bypass;
|
||||
int dis_dyn_adr_tri;
|
||||
int phy_mstr_train_interval;
|
||||
int phy_mstr_max_req_to_ack;
|
||||
int wdqsext;
|
||||
int cal_interval;
|
||||
int cal_once;
|
||||
int dram_byte_swap;
|
||||
int rx_en_back_off;
|
||||
int train_sequence_ctrl;
|
||||
int phy_gen2_umctl_opt;
|
||||
int phy_gen2_umctl_f0rc5x;
|
||||
int tx_slew_rise_dq;
|
||||
int tx_slew_fall_dq;
|
||||
int tx_slew_rise_ac;
|
||||
int tx_slew_fall_ac;
|
||||
int enable_high_clk_skew_fix;
|
||||
int disable_unused_addr_lns;
|
||||
int phy_init_sequence_num;
|
||||
int cs_mode; /* rdimm */
|
||||
int cast_cs_to_cid; /* rdimm */
|
||||
};
|
||||
|
||||
struct input {
|
||||
struct input_basic basic;
|
||||
struct input_advanced adv;
|
||||
unsigned int mr[7];
|
||||
unsigned int cs_d0;
|
||||
unsigned int cs_d1;
|
||||
unsigned int mirror;
|
||||
unsigned int odt[4];
|
||||
unsigned int rcw[16];
|
||||
unsigned int rcw3x;
|
||||
unsigned int vref;
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,334 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#if !defined(PHY_H) && defined(NXP_WARM_BOOT)
|
||||
#define PHY_H
|
||||
|
||||
#include <flash_info.h>
|
||||
|
||||
/* To store sector size to be erase on flash*/
|
||||
#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
|
||||
|
||||
/*Structure to implement address-data map tuples to store PHY training values*/
|
||||
struct phy_training_values {
|
||||
uint32_t addr;
|
||||
uint16_t data;
|
||||
};
|
||||
/* Saves PHY Training Register values after cold reset
|
||||
*@param[in] phy_ptr array to store addresses of PHYs
|
||||
*@param[in] address_to_store address to save PHY training register values
|
||||
*on flash
|
||||
*@param[in] num_of_phy the number of PHY for which training values are
|
||||
*to be saved
|
||||
*@param[in] train2d flag to store whether 2D training registers are to
|
||||
*be saved or not
|
||||
*
|
||||
*PHY training values will be stored on flash at contigous memory in the order:
|
||||
*1D training registers, 2D training registers
|
||||
*for each PHY
|
||||
*
|
||||
*if train2d is false saving 2D training registers will be skipped
|
||||
*/
|
||||
int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
|
||||
uint32_t num_of_phy, int train2d);
|
||||
|
||||
/*Restores PHY Training Register values after warm reset
|
||||
*@param[in] phy_ptr array to store addresses of PHYs
|
||||
*@param[in] address_to_store address to retrieve PHY training register
|
||||
*values from flash
|
||||
*@param[in] num_of_phy the number of PHY for which training values are
|
||||
*to be restored
|
||||
*@param[in] train2d flag to store whether 2D training registers are
|
||||
*to be restored or not
|
||||
*
|
||||
*if train2d is false saving 2D training registers will be skipped
|
||||
*/
|
||||
|
||||
int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
|
||||
uint32_t num_of_phy, int train2d);
|
||||
|
||||
/*
|
||||
* Address data tuples to store the PHY 1D
|
||||
*/
|
||||
|
||||
struct phy_training_values training_1D_values[] = {
|
||||
{0x200B2, 0}, {0x200CB, 0}, {0x10043, 0}, {0x11043, 0},
|
||||
{0x12043, 0}, {0x13043, 0}, {0x14043, 0}, {0x15043, 0},
|
||||
{0x16043, 0}, {0x17043, 0}, {0x18043, 0}, {0x10143, 0},
|
||||
{0x11143, 0}, {0x12143, 0}, {0x13143, 0}, {0x14143, 0},
|
||||
{0x15143, 0}, {0x16143, 0}, {0x17143, 0}, {0x18143, 0},
|
||||
{0x10080, 0}, {0x11080, 0}, {0x12080, 0}, {0x13080, 0},
|
||||
{0x14080, 0}, {0x15080, 0}, {0x16080, 0}, {0x17080, 0},
|
||||
{0x18080, 0}, {0x10180, 0}, {0x11180, 0}, {0x12180, 0},
|
||||
{0x13180, 0}, {0x14180, 0}, {0x15180, 0}, {0x16180, 0},
|
||||
{0x17180, 0}, {0x18180, 0}, {0x10081, 0}, {0x11081, 0},
|
||||
{0x12081, 0}, {0x13081, 0}, {0x14081, 0}, {0x15081, 0},
|
||||
{0x16081, 0}, {0x17081, 0}, {0x18081, 0}, {0x10181, 0},
|
||||
{0x11181, 0}, {0x12181, 0}, {0x13181, 0}, {0x14181, 0},
|
||||
{0x15181, 0}, {0x16181, 0}, {0x17181, 0}, {0x18181, 0},
|
||||
{0x10082, 0}, {0x11082, 0}, {0x12082, 0}, {0x13082, 0},
|
||||
{0x14082, 0}, {0x15082, 0}, {0x16082, 0}, {0x17082, 0},
|
||||
{0x18082, 0}, {0x10182, 0}, {0x11182, 0}, {0x12182, 0},
|
||||
{0x13182, 0}, {0x14182, 0}, {0x15182, 0}, {0x16182, 0},
|
||||
{0x17182, 0}, {0x18182, 0}, {0x10083, 0}, {0x11083, 0},
|
||||
{0x12083, 0}, {0x13083, 0}, {0x14083, 0}, {0x15083, 0},
|
||||
{0x16083, 0}, {0x17083, 0}, {0x18083, 0}, {0x10183, 0},
|
||||
{0x11183, 0}, {0x12183, 0}, {0x13183, 0}, {0x14183, 0},
|
||||
{0x15183, 0}, {0x16183, 0}, {0x17183, 0}, {0x18183, 0},
|
||||
{0x100D0, 0}, {0x110D0, 0}, {0x120D0, 0}, {0x130D0, 0},
|
||||
{0x140D0, 0}, {0x150D0, 0}, {0x160D0, 0}, {0x170D0, 0},
|
||||
{0x180D0, 0}, {0x101D0, 0}, {0x111D0, 0}, {0x121D0, 0},
|
||||
{0x131D0, 0}, {0x141D0, 0}, {0x151D0, 0}, {0x161D0, 0},
|
||||
{0x171D0, 0}, {0x181D0, 0}, {0x100D1, 0}, {0x110D1, 0},
|
||||
{0x120D1, 0}, {0x130D1, 0}, {0x140D1, 0}, {0x150D1, 0},
|
||||
{0x160D1, 0}, {0x170D1, 0}, {0x180D1, 0}, {0x101D1, 0},
|
||||
{0x111D1, 0}, {0x121D1, 0}, {0x131D1, 0}, {0x141D1, 0},
|
||||
{0x151D1, 0}, {0x161D1, 0}, {0x171D1, 0}, {0x181D1, 0},
|
||||
{0x100D2, 0}, {0x110D2, 0}, {0x120D2, 0}, {0x130D2, 0},
|
||||
{0x140D2, 0}, {0x150D2, 0}, {0x160D2, 0}, {0x170D2, 0},
|
||||
{0x180D2, 0}, {0x101D2, 0}, {0x111D2, 0}, {0x121D2, 0},
|
||||
{0x131D2, 0}, {0x141D2, 0}, {0x151D2, 0}, {0x161D2, 0},
|
||||
{0x171D2, 0}, {0x181D2, 0}, {0x100D3, 0}, {0x110D3, 0},
|
||||
{0x120D3, 0}, {0x130D3, 0}, {0x140D3, 0}, {0x150D3, 0},
|
||||
{0x160D3, 0}, {0x170D3, 0}, {0x180D3, 0}, {0x101D3, 0},
|
||||
{0x111D3, 0}, {0x121D3, 0}, {0x131D3, 0}, {0x141D3, 0},
|
||||
{0x151D3, 0}, {0x161D3, 0}, {0x171D3, 0}, {0x181D3, 0},
|
||||
{0x10068, 0}, {0x11068, 0}, {0x12068, 0}, {0x13068, 0},
|
||||
{0x14068, 0}, {0x15068, 0}, {0x16068, 0}, {0x17068, 0},
|
||||
{0x18068, 0}, {0x10168, 0}, {0x11168, 0}, {0x12168, 0},
|
||||
{0x13168, 0}, {0x14168, 0}, {0x15168, 0}, {0x16168, 0},
|
||||
{0x17168, 0}, {0x18168, 0}, {0x10268, 0}, {0x11268, 0},
|
||||
{0x12268, 0}, {0x13268, 0}, {0x14268, 0}, {0x15268, 0},
|
||||
{0x16268, 0}, {0x17268, 0}, {0x18268, 0}, {0x10368, 0},
|
||||
{0x11368, 0}, {0x12368, 0}, {0x13368, 0}, {0x14368, 0},
|
||||
{0x15368, 0}, {0x16368, 0}, {0x17368, 0}, {0x18368, 0},
|
||||
{0x10468, 0}, {0x11468, 0}, {0x12468, 0}, {0x13468, 0},
|
||||
{0x14468, 0}, {0x15468, 0}, {0x16468, 0}, {0x17468, 0},
|
||||
{0x18468, 0}, {0x10568, 0}, {0x11568, 0}, {0x12568, 0},
|
||||
{0x13568, 0}, {0x14568, 0}, {0x15568, 0}, {0x16568, 0},
|
||||
{0x17568, 0}, {0x18568, 0}, {0x10668, 0}, {0x11668, 0},
|
||||
{0x12668, 0}, {0x13668, 0}, {0x14668, 0}, {0x15668, 0},
|
||||
{0x16668, 0}, {0x17668, 0}, {0x18668, 0}, {0x10768, 0},
|
||||
{0x11768, 0}, {0x12768, 0}, {0x13768, 0}, {0x14768, 0},
|
||||
{0x15768, 0}, {0x16768, 0}, {0x17768, 0}, {0x18768, 0},
|
||||
{0x10868, 0}, {0x11868, 0}, {0x12868, 0}, {0x13868, 0},
|
||||
{0x14868, 0}, {0x15868, 0}, {0x16868, 0}, {0x17868, 0},
|
||||
{0x18868, 0}, {0x10069, 0}, {0x11069, 0}, {0x12069, 0},
|
||||
{0x13069, 0}, {0x14069, 0}, {0x15069, 0}, {0x16069, 0},
|
||||
{0x17069, 0}, {0x18069, 0}, {0x10169, 0}, {0x11169, 0},
|
||||
{0x12169, 0}, {0x13169, 0}, {0x14169, 0}, {0x15169, 0},
|
||||
{0x16169, 0}, {0x17169, 0}, {0x18169, 0}, {0x10269, 0},
|
||||
{0x11269, 0}, {0x12269, 0}, {0x13269, 0}, {0x14269, 0},
|
||||
{0x15269, 0}, {0x16269, 0}, {0x17269, 0}, {0x18269, 0},
|
||||
{0x10369, 0}, {0x11369, 0}, {0x12369, 0}, {0x13369, 0},
|
||||
{0x14369, 0}, {0x15369, 0}, {0x16369, 0}, {0x17369, 0},
|
||||
{0x18369, 0}, {0x10469, 0}, {0x11469, 0}, {0x12469, 0},
|
||||
{0x13469, 0}, {0x14469, 0}, {0x15469, 0}, {0x16469, 0},
|
||||
{0x17469, 0}, {0x18469, 0}, {0x10569, 0}, {0x11569, 0},
|
||||
{0x12569, 0}, {0x13569, 0}, {0x14569, 0}, {0x15569, 0},
|
||||
{0x16569, 0}, {0x17569, 0}, {0x18569, 0}, {0x10669, 0},
|
||||
{0x11669, 0}, {0x12669, 0}, {0x13669, 0}, {0x14669, 0},
|
||||
{0x15669, 0}, {0x16669, 0}, {0x17669, 0}, {0x18669, 0},
|
||||
{0x10769, 0}, {0x11769, 0}, {0x12769, 0}, {0x13769, 0},
|
||||
{0x14769, 0}, {0x15769, 0}, {0x16769, 0}, {0x17769, 0},
|
||||
{0x18769, 0}, {0x10869, 0}, {0x11869, 0}, {0x12869, 0},
|
||||
{0x13869, 0}, {0x14869, 0}, {0x15869, 0}, {0x16869, 0},
|
||||
{0x17869, 0}, {0x18869, 0}, {0x1006A, 0}, {0x1106A, 0},
|
||||
{0x1206A, 0}, {0x1306A, 0}, {0x1406A, 0}, {0x1506A, 0},
|
||||
{0x1606A, 0}, {0x1706A, 0}, {0x1806A, 0}, {0x1016A, 0},
|
||||
{0x1116A, 0}, {0x1216A, 0}, {0x1316A, 0}, {0x1416A, 0},
|
||||
{0x1516A, 0}, {0x1616A, 0}, {0x1716A, 0}, {0x1816A, 0},
|
||||
{0x1026A, 0}, {0x1126A, 0}, {0x1226A, 0}, {0x1326A, 0},
|
||||
{0x1426A, 0}, {0x1526A, 0}, {0x1626A, 0}, {0x1726A, 0},
|
||||
{0x1826A, 0}, {0x1036A, 0}, {0x1136A, 0}, {0x1236A, 0},
|
||||
{0x1336A, 0}, {0x1436A, 0}, {0x1536A, 0}, {0x1636A, 0},
|
||||
{0x1736A, 0}, {0x1836A, 0}, {0x1046A, 0}, {0x1146A, 0},
|
||||
{0x1246A, 0}, {0x1346A, 0}, {0x1446A, 0}, {0x1546A, 0},
|
||||
{0x1646A, 0}, {0x1746A, 0}, {0x1846A, 0}, {0x1056A, 0},
|
||||
{0x1156A, 0}, {0x1256A, 0}, {0x1356A, 0}, {0x1456A, 0},
|
||||
{0x1556A, 0}, {0x1656A, 0}, {0x1756A, 0}, {0x1856A, 0},
|
||||
{0x1066A, 0}, {0x1166A, 0}, {0x1266A, 0}, {0x1366A, 0},
|
||||
{0x1466A, 0}, {0x1566A, 0}, {0x1666A, 0}, {0x1766A, 0},
|
||||
{0x1866A, 0}, {0x1076A, 0}, {0x1176A, 0}, {0x1276A, 0},
|
||||
{0x1376A, 0}, {0x1476A, 0}, {0x1576A, 0}, {0x1676A, 0},
|
||||
{0x1776A, 0}, {0x1876A, 0}, {0x1086A, 0}, {0x1186A, 0},
|
||||
{0x1286A, 0}, {0x1386A, 0}, {0x1486A, 0}, {0x1586A, 0},
|
||||
{0x1686A, 0}, {0x1786A, 0}, {0x1886A, 0}, {0x1006B, 0},
|
||||
{0x1106B, 0}, {0x1206B, 0}, {0x1306B, 0}, {0x1406B, 0},
|
||||
{0x1506B, 0}, {0x1606B, 0}, {0x1706B, 0}, {0x1806B, 0},
|
||||
{0x1016B, 0}, {0x1116B, 0}, {0x1216B, 0}, {0x1316B, 0},
|
||||
{0x1416B, 0}, {0x1516B, 0}, {0x1616B, 0}, {0x1716B, 0},
|
||||
{0x1816B, 0}, {0x1026B, 0}, {0x1126B, 0}, {0x1226B, 0},
|
||||
{0x1326B, 0}, {0x1426B, 0}, {0x1526B, 0}, {0x1626B, 0},
|
||||
{0x1726B, 0}, {0x1826B, 0}, {0x1036B, 0}, {0x1136B, 0},
|
||||
{0x1236B, 0}, {0x1336B, 0}, {0x1436B, 0}, {0x1536B, 0},
|
||||
{0x1636B, 0}, {0x1736B, 0}, {0x1836B, 0}, {0x1046B, 0},
|
||||
{0x1146B, 0}, {0x1246B, 0}, {0x1346B, 0}, {0x1446B, 0},
|
||||
{0x1546B, 0}, {0x1646B, 0}, {0x1746B, 0}, {0x1846B, 0},
|
||||
{0x1056B, 0}, {0x1156B, 0}, {0x1256B, 0}, {0x1356B, 0},
|
||||
{0x1456B, 0}, {0x1556B, 0}, {0x1656B, 0}, {0x1756B, 0},
|
||||
{0x1856B, 0}, {0x1066B, 0}, {0x1166B, 0}, {0x1266B, 0},
|
||||
{0x1366B, 0}, {0x1466B, 0}, {0x1566B, 0}, {0x1666B, 0},
|
||||
{0x1766B, 0}, {0x1866B, 0}, {0x1076B, 0}, {0x1176B, 0},
|
||||
{0x1276B, 0}, {0x1376B, 0}, {0x1476B, 0}, {0x1576B, 0},
|
||||
{0x1676B, 0}, {0x1776B, 0}, {0x1876B, 0}, {0x1086B, 0},
|
||||
{0x1186B, 0}, {0x1286B, 0}, {0x1386B, 0}, {0x1486B, 0},
|
||||
{0x1586B, 0}, {0x1686B, 0}, {0x1786B, 0}, {0x1886B, 0},
|
||||
{0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0},
|
||||
{0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0},
|
||||
{0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0},
|
||||
{0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0},
|
||||
{0x1718C, 0}, {0x1818C, 0}, {0x1008D, 0}, {0x1108D, 0},
|
||||
{0x1208D, 0}, {0x1308D, 0}, {0x1408D, 0}, {0x1508D, 0},
|
||||
{0x1608D, 0}, {0x1708D, 0}, {0x1808D, 0}, {0x1018D, 0},
|
||||
{0x1118D, 0}, {0x1218D, 0}, {0x1318D, 0}, {0x1418D, 0},
|
||||
{0x1518D, 0}, {0x1618D, 0}, {0x1718D, 0}, {0x1818D, 0},
|
||||
{0x1008E, 0}, {0x1108E, 0}, {0x1208E, 0}, {0x1308E, 0},
|
||||
{0x1408E, 0}, {0x1508E, 0}, {0x1608E, 0}, {0x1708E, 0},
|
||||
{0x1808E, 0}, {0x1018E, 0}, {0x1118E, 0}, {0x1218E, 0},
|
||||
{0x1318E, 0}, {0x1418E, 0}, {0x1518E, 0}, {0x1618E, 0},
|
||||
{0x1718E, 0}, {0x1818E, 0}, {0x1008F, 0}, {0x1108F, 0},
|
||||
{0x1208F, 0}, {0x1308F, 0}, {0x1408F, 0}, {0x1508F, 0},
|
||||
{0x1608F, 0}, {0x1708F, 0}, {0x1808F, 0}, {0x1018F, 0},
|
||||
{0x1118F, 0}, {0x1218F, 0}, {0x1318F, 0}, {0x1418F, 0},
|
||||
{0x1518F, 0}, {0x1618F, 0}, {0x1718F, 0}, {0x1818F, 0},
|
||||
{0x100C0, 0}, {0x110C0, 0}, {0x120C0, 0}, {0x130C0, 0},
|
||||
{0x140C0, 0}, {0x150C0, 0}, {0x160C0, 0}, {0x170C0, 0},
|
||||
{0x180C0, 0}, {0x101C0, 0}, {0x111C0, 0}, {0x121C0, 0},
|
||||
{0x131C0, 0}, {0x141C0, 0}, {0x151C0, 0}, {0x161C0, 0},
|
||||
{0x171C0, 0}, {0x181C0, 0}, {0x102C0, 0}, {0x112C0, 0},
|
||||
{0x122C0, 0}, {0x132C0, 0}, {0x142C0, 0}, {0x152C0, 0},
|
||||
{0x162C0, 0}, {0x172C0, 0}, {0x182C0, 0}, {0x103C0, 0},
|
||||
{0x113C0, 0}, {0x123C0, 0}, {0x133C0, 0}, {0x143C0, 0},
|
||||
{0x153C0, 0}, {0x163C0, 0}, {0x173C0, 0}, {0x183C0, 0},
|
||||
{0x104C0, 0}, {0x114C0, 0}, {0x124C0, 0}, {0x134C0, 0},
|
||||
{0x144C0, 0}, {0x154C0, 0}, {0x164C0, 0}, {0x174C0, 0},
|
||||
{0x184C0, 0}, {0x105C0, 0}, {0x115C0, 0}, {0x125C0, 0},
|
||||
{0x135C0, 0}, {0x145C0, 0}, {0x155C0, 0}, {0x165C0, 0},
|
||||
{0x175C0, 0}, {0x185C0, 0}, {0x106C0, 0}, {0x116C0, 0},
|
||||
{0x126C0, 0}, {0x136C0, 0}, {0x146C0, 0}, {0x156C0, 0},
|
||||
{0x166C0, 0}, {0x176C0, 0}, {0x186C0, 0}, {0x107C0, 0},
|
||||
{0x117C0, 0}, {0x127C0, 0}, {0x137C0, 0}, {0x147C0, 0},
|
||||
{0x157C0, 0}, {0x167C0, 0}, {0x177C0, 0}, {0x187C0, 0},
|
||||
{0x108C0, 0}, {0x118C0, 0}, {0x128C0, 0}, {0x138C0, 0},
|
||||
{0x148C0, 0}, {0x158C0, 0}, {0x168C0, 0}, {0x178C0, 0},
|
||||
{0x188C0, 0}, {0x100C1, 0}, {0x110C1, 0}, {0x120C1, 0},
|
||||
{0x130C1, 0}, {0x140C1, 0}, {0x150C1, 0}, {0x160C1, 0},
|
||||
{0x170C1, 0}, {0x180C1, 0}, {0x101C1, 0}, {0x111C1, 0},
|
||||
{0x121C1, 0}, {0x131C1, 0}, {0x141C1, 0}, {0x151C1, 0},
|
||||
{0x161C1, 0}, {0x171C1, 0}, {0x181C1, 0}, {0x102C1, 0},
|
||||
{0x112C1, 0}, {0x122C1, 0}, {0x132C1, 0}, {0x142C1, 0},
|
||||
{0x152C1, 0}, {0x162C1, 0}, {0x172C1, 0}, {0x182C1, 0},
|
||||
{0x103C1, 0}, {0x113C1, 0}, {0x123C1, 0}, {0x133C1, 0},
|
||||
{0x143C1, 0}, {0x153C1, 0}, {0x163C1, 0}, {0x173C1, 0},
|
||||
{0x183C1, 0}, {0x104C1, 0}, {0x114C1, 0}, {0x124C1, 0},
|
||||
{0x134C1, 0}, {0x144C1, 0}, {0x154C1, 0}, {0x164C1, 0},
|
||||
{0x174C1, 0}, {0x184C1, 0}, {0x105C1, 0}, {0x115C1, 0},
|
||||
{0x125C1, 0}, {0x135C1, 0}, {0x145C1, 0}, {0x155C1, 0},
|
||||
{0x165C1, 0}, {0x175C1, 0}, {0x185C1, 0}, {0x106C1, 0},
|
||||
{0x116C1, 0}, {0x126C1, 0}, {0x136C1, 0}, {0x146C1, 0},
|
||||
{0x156C1, 0}, {0x166C1, 0}, {0x176C1, 0}, {0x186C1, 0},
|
||||
{0x107C1, 0}, {0x117C1, 0}, {0x127C1, 0}, {0x137C1, 0},
|
||||
{0x147C1, 0}, {0x157C1, 0}, {0x167C1, 0}, {0x177C1, 0},
|
||||
{0x187C1, 0}, {0x108C1, 0}, {0x118C1, 0}, {0x128C1, 0},
|
||||
{0x138C1, 0}, {0x148C1, 0}, {0x158C1, 0}, {0x168C1, 0},
|
||||
{0x178C1, 0}, {0x188C1, 0}, {0x100C2, 0}, {0x110C2, 0},
|
||||
{0x120C2, 0}, {0x130C2, 0}, {0x140C2, 0}, {0x150C2, 0},
|
||||
{0x160C2, 0}, {0x170C2, 0}, {0x180C2, 0}, {0x101C2, 0},
|
||||
{0x111C2, 0}, {0x121C2, 0}, {0x131C2, 0}, {0x141C2, 0},
|
||||
{0x151C2, 0}, {0x161C2, 0}, {0x171C2, 0}, {0x181C2, 0},
|
||||
{0x102C2, 0}, {0x112C2, 0}, {0x122C2, 0}, {0x132C2, 0},
|
||||
{0x142C2, 0}, {0x152C2, 0}, {0x162C2, 0}, {0x172C2, 0},
|
||||
{0x182C2, 0}, {0x103C2, 0}, {0x113C2, 0}, {0x123C2, 0},
|
||||
{0x133C2, 0}, {0x143C2, 0}, {0x153C2, 0}, {0x163C2, 0},
|
||||
{0x173C2, 0}, {0x183C2, 0}, {0x104C2, 0}, {0x114C2, 0},
|
||||
{0x124C2, 0}, {0x134C2, 0}, {0x144C2, 0}, {0x154C2, 0},
|
||||
{0x164C2, 0}, {0x174C2, 0}, {0x184C2, 0}, {0x105C2, 0},
|
||||
{0x115C2, 0}, {0x125C2, 0}, {0x135C2, 0}, {0x145C2, 0},
|
||||
{0x155C2, 0}, {0x165C2, 0}, {0x175C2, 0}, {0x185C2, 0},
|
||||
{0x106C2, 0}, {0x116C2, 0}, {0x126C2, 0}, {0x136C2, 0},
|
||||
{0x146C2, 0}, {0x156C2, 0}, {0x166C2, 0}, {0x176C2, 0},
|
||||
{0x186C2, 0}, {0x107C2, 0}, {0x117C2, 0}, {0x127C2, 0},
|
||||
{0x137C2, 0}, {0x147C2, 0}, {0x157C2, 0}, {0x167C2, 0},
|
||||
{0x177C2, 0}, {0x187C2, 0}, {0x108C2, 0}, {0x118C2, 0},
|
||||
{0x128C2, 0}, {0x138C2, 0}, {0x148C2, 0}, {0x158C2, 0},
|
||||
{0x168C2, 0}, {0x178C2, 0}, {0x188C2, 0}, {0x100C3, 0},
|
||||
{0x110C3, 0}, {0x120C3, 0}, {0x130C3, 0}, {0x140C3, 0},
|
||||
{0x150C3, 0}, {0x160C3, 0}, {0x170C3, 0}, {0x180C3, 0},
|
||||
{0x101C3, 0}, {0x111C3, 0}, {0x121C3, 0}, {0x131C3, 0},
|
||||
{0x141C3, 0}, {0x151C3, 0}, {0x161C3, 0}, {0x171C3, 0},
|
||||
{0x181C3, 0}, {0x102C3, 0}, {0x112C3, 0}, {0x122C3, 0},
|
||||
{0x132C3, 0}, {0x142C3, 0}, {0x152C3, 0}, {0x162C3, 0},
|
||||
{0x172C3, 0}, {0x182C3, 0}, {0x103C3, 0}, {0x113C3, 0},
|
||||
{0x123C3, 0}, {0x133C3, 0}, {0x143C3, 0}, {0x153C3, 0},
|
||||
{0x163C3, 0}, {0x173C3, 0}, {0x183C3, 0}, {0x104C3, 0},
|
||||
{0x114C3, 0}, {0x124C3, 0}, {0x134C3, 0}, {0x144C3, 0},
|
||||
{0x154C3, 0}, {0x164C3, 0}, {0x174C3, 0}, {0x184C3, 0},
|
||||
{0x105C3, 0}, {0x115C3, 0}, {0x125C3, 0}, {0x135C3, 0},
|
||||
{0x145C3, 0}, {0x155C3, 0}, {0x165C3, 0}, {0x175C3, 0},
|
||||
{0x185C3, 0}, {0x106C3, 0}, {0x116C3, 0}, {0x126C3, 0},
|
||||
{0x136C3, 0}, {0x146C3, 0}, {0x156C3, 0}, {0x166C3, 0},
|
||||
{0x176C3, 0}, {0x186C3, 0}, {0x107C3, 0}, {0x117C3, 0},
|
||||
{0x127C3, 0}, {0x137C3, 0}, {0x147C3, 0}, {0x157C3, 0},
|
||||
{0x167C3, 0}, {0x177C3, 0}, {0x187C3, 0}, {0x108C3, 0},
|
||||
{0x118C3, 0}, {0x128C3, 0}, {0x138C3, 0}, {0x148C3, 0},
|
||||
{0x158C3, 0}, {0x168C3, 0}, {0x178C3, 0}, {0x188C3, 0},
|
||||
{0x10020, 0}, {0x11020, 0}, {0x12020, 0}, {0x13020, 0},
|
||||
{0x14020, 0}, {0x15020, 0}, {0x16020, 0}, {0x17020, 0},
|
||||
{0x18020, 0}, {0x2007D, 0}, {0x20077, 0}
|
||||
};
|
||||
|
||||
/*
|
||||
*Array to store the PHY 2D Training register addresses
|
||||
*/
|
||||
struct phy_training_values training_2D_values[] = {
|
||||
{0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0},
|
||||
{0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0},
|
||||
{0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0},
|
||||
{0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0},
|
||||
{0x1718C, 0}, {0x1818C, 0}, {0x10040, 0}, {0x11040, 0},
|
||||
{0x12040, 0}, {0x13040, 0}, {0x14040, 0}, {0x15040, 0},
|
||||
{0x16040, 0}, {0x17040, 0}, {0x18040, 0}, {0x10140, 0},
|
||||
{0x11140, 0}, {0x12140, 0}, {0x13140, 0}, {0x14140, 0},
|
||||
{0x15140, 0}, {0x16140, 0}, {0x17140, 0}, {0x18140, 0},
|
||||
{0x10240, 0}, {0x11240, 0}, {0x12240, 0}, {0x13240, 0},
|
||||
{0x14240, 0}, {0x15240, 0}, {0x16240, 0}, {0x17240, 0},
|
||||
{0x18240, 0}, {0x10340, 0}, {0x11340, 0}, {0x12340, 0},
|
||||
{0x13340, 0}, {0x14340, 0}, {0x15340, 0}, {0x16340, 0},
|
||||
{0x17340, 0}, {0x18340, 0}, {0x10440, 0}, {0x11440, 0},
|
||||
{0x12440, 0}, {0x13440, 0}, {0x14440, 0}, {0x15440, 0},
|
||||
{0x16440, 0}, {0x17440, 0}, {0x18440, 0}, {0x10540, 0},
|
||||
{0x11540, 0}, {0x12540, 0}, {0x13540, 0}, {0x14540, 0},
|
||||
{0x15540, 0}, {0x16540, 0}, {0x17540, 0}, {0x18540, 0},
|
||||
{0x10640, 0}, {0x11640, 0}, {0x12640, 0}, {0x13640, 0},
|
||||
{0x14640, 0}, {0x15640, 0}, {0x16640, 0}, {0x17640, 0},
|
||||
{0x18640, 0}, {0x10740, 0}, {0x11740, 0}, {0x12740, 0},
|
||||
{0x13740, 0}, {0x14740, 0}, {0x15740, 0}, {0x16740, 0},
|
||||
{0x17740, 0}, {0x18740, 0}, {0x10840, 0}, {0x11840, 0},
|
||||
{0x12840, 0}, {0x13840, 0}, {0x14840, 0}, {0x15840, 0},
|
||||
{0x16840, 0}, {0x17840, 0}, {0x18840, 0}, {0x10030, 0},
|
||||
{0x11030, 0}, {0x12030, 0}, {0x13030, 0}, {0x14030, 0},
|
||||
{0x15030, 0}, {0x16030, 0}, {0x17030, 0}, {0x18030, 0},
|
||||
{0x10130, 0}, {0x11130, 0}, {0x12130, 0}, {0x13130, 0},
|
||||
{0x14130, 0}, {0x15130, 0}, {0x16130, 0}, {0x17130, 0},
|
||||
{0x18130, 0}, {0x10230, 0}, {0x11230, 0}, {0x12230, 0},
|
||||
{0x13230, 0}, {0x14230, 0}, {0x15230, 0}, {0x16230, 0},
|
||||
{0x17230, 0}, {0x18230, 0}, {0x10330, 0}, {0x11330, 0},
|
||||
{0x12330, 0}, {0x13330, 0}, {0x14330, 0}, {0x15330, 0},
|
||||
{0x16330, 0}, {0x17330, 0}, {0x18330, 0}, {0x10430, 0},
|
||||
{0x11430, 0}, {0x12430, 0}, {0x13430, 0}, {0x14430, 0},
|
||||
{0x15430, 0}, {0x16430, 0}, {0x17430, 0}, {0x18430, 0},
|
||||
{0x10530, 0}, {0x11530, 0}, {0x12530, 0}, {0x13530, 0},
|
||||
{0x14530, 0}, {0x15530, 0}, {0x16530, 0}, {0x17530, 0},
|
||||
{0x18530, 0}, {0x10630, 0}, {0x11630, 0}, {0x12630, 0},
|
||||
{0x13630, 0}, {0x14630, 0}, {0x15630, 0}, {0x16630, 0},
|
||||
{0x17630, 0}, {0x18630, 0}, {0x10730, 0}, {0x11730, 0},
|
||||
{0x12730, 0}, {0x13730, 0}, {0x14730, 0}, {0x15730, 0},
|
||||
{0x16730, 0}, {0x17730, 0}, {0x18730, 0}, {0x10830, 0},
|
||||
{0x11830, 0}, {0x12830, 0}, {0x13830, 0}, {0x14830, 0},
|
||||
{0x15830, 0}, {0x16830, 0}, {0x17830, 0}, {0x18830, 0}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,632 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PIE_H
|
||||
#define PIE_H
|
||||
|
||||
struct pie {
|
||||
uint32_t addr;
|
||||
uint16_t data;
|
||||
};
|
||||
|
||||
static const struct pie pie_udimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x90029, 0xb},
|
||||
{0x9002a, 0x480},
|
||||
{0x9002b, 0x109},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x448},
|
||||
{0x9002e, 0x139},
|
||||
{0x9002f, 0x8},
|
||||
{0x90030, 0x478},
|
||||
{0x90031, 0x109},
|
||||
{0x90032, 0x2},
|
||||
{0x90033, 0x10},
|
||||
{0x90034, 0x139},
|
||||
{0x90035, 0xb},
|
||||
{0x90036, 0x7c0},
|
||||
{0x90037, 0x139},
|
||||
{0x90038, 0x44},
|
||||
{0x90039, 0x633},
|
||||
{0x9003a, 0x159},
|
||||
{0x9003b, 0x14f},
|
||||
{0x9003c, 0x630},
|
||||
{0x9003d, 0x159},
|
||||
{0x9003e, 0x47},
|
||||
{0x9003f, 0x633},
|
||||
{0x90040, 0x149},
|
||||
{0x90041, 0x4f},
|
||||
{0x90042, 0x633},
|
||||
{0x90043, 0x179},
|
||||
{0x90044, 0x8},
|
||||
{0x90045, 0xe0},
|
||||
{0x90046, 0x109},
|
||||
{0x90047, 0x0},
|
||||
{0x90048, 0x7c8},
|
||||
{0x90049, 0x109},
|
||||
{0x9004a, 0x0},
|
||||
{0x9004b, 0x1},
|
||||
{0x9004c, 0x8},
|
||||
{0x9004d, 0x0},
|
||||
{0x9004e, 0x45a},
|
||||
{0x9004f, 0x9},
|
||||
{0x90050, 0x0},
|
||||
{0x90051, 0x448},
|
||||
{0x90052, 0x109},
|
||||
{0x90053, 0x40},
|
||||
{0x90054, 0x633},
|
||||
{0x90055, 0x179},
|
||||
{0x90056, 0x1},
|
||||
{0x90057, 0x618},
|
||||
{0x90058, 0x109},
|
||||
{0x90059, 0x40c0},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x149},
|
||||
{0x9005c, 0x8},
|
||||
{0x9005d, 0x4},
|
||||
{0x9005e, 0x48},
|
||||
{0x9005f, 0x4040},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x0},
|
||||
{0x90063, 0x4},
|
||||
{0x90064, 0x48},
|
||||
{0x90065, 0x40},
|
||||
{0x90066, 0x633},
|
||||
{0x90067, 0x149},
|
||||
{0x90068, 0x10},
|
||||
{0x90069, 0x4},
|
||||
{0x9006a, 0x18},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x4},
|
||||
{0x9006d, 0x78},
|
||||
{0x9006e, 0x549},
|
||||
{0x9006f, 0x633},
|
||||
{0x90070, 0x159},
|
||||
{0x90071, 0xd49},
|
||||
{0x90072, 0x633},
|
||||
{0x90073, 0x159},
|
||||
{0x90074, 0x94a},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x159},
|
||||
{0x90077, 0x441},
|
||||
{0x90078, 0x633},
|
||||
{0x90079, 0x149},
|
||||
{0x9007a, 0x42},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x1},
|
||||
{0x9007e, 0x633},
|
||||
{0x9007f, 0x149},
|
||||
{0x90080, 0x0},
|
||||
{0x90081, 0xe0},
|
||||
{0x90082, 0x109},
|
||||
{0x90083, 0xa},
|
||||
{0x90084, 0x10},
|
||||
{0x90085, 0x109},
|
||||
{0x90086, 0x9},
|
||||
{0x90087, 0x3c0},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x9},
|
||||
{0x9008a, 0x3c0},
|
||||
{0x9008b, 0x159},
|
||||
{0x9008c, 0x18},
|
||||
{0x9008d, 0x10},
|
||||
{0x9008e, 0x109},
|
||||
{0x9008f, 0x0},
|
||||
{0x90090, 0x3c0},
|
||||
{0x90091, 0x109},
|
||||
{0x90092, 0x18},
|
||||
{0x90093, 0x4},
|
||||
{0x90094, 0x48},
|
||||
{0x90095, 0x18},
|
||||
{0x90096, 0x4},
|
||||
{0x90097, 0x58},
|
||||
{0x90098, 0xb},
|
||||
{0x90099, 0x10},
|
||||
{0x9009a, 0x109},
|
||||
{0x9009b, 0x1},
|
||||
{0x9009c, 0x10},
|
||||
{0x9009d, 0x109},
|
||||
{0x9009e, 0x5},
|
||||
{0x9009f, 0x7c0},
|
||||
{0x900a0, 0x109},
|
||||
{0x900a1, 0x0},
|
||||
{0x900a2, 0x8140},
|
||||
{0x900a3, 0x10c},
|
||||
{0x900a4, 0x10},
|
||||
{0x900a5, 0x8138},
|
||||
{0x900a6, 0x10c},
|
||||
{0x900a7, 0x8},
|
||||
{0x900a8, 0x7c8},
|
||||
{0x900a9, 0x101},
|
||||
{0x900aa, 0x8},
|
||||
{0x900ab, 0x448},
|
||||
{0x900ac, 0x109},
|
||||
{0x900ad, 0xf},
|
||||
{0x900ae, 0x7c0},
|
||||
{0x900af, 0x109},
|
||||
{0x900b0, 0x47},
|
||||
{0x900b1, 0x630},
|
||||
{0x900b2, 0x109},
|
||||
{0x900b3, 0x8},
|
||||
{0x900b4, 0x618},
|
||||
{0x900b5, 0x109},
|
||||
{0x900b6, 0x8},
|
||||
{0x900b7, 0xe0},
|
||||
{0x900b8, 0x109},
|
||||
{0x900b9, 0x0},
|
||||
{0x900ba, 0x7c8},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x8},
|
||||
{0x900bd, 0x8140},
|
||||
{0x900be, 0x10c},
|
||||
{0x900bf, 0x0},
|
||||
{0x900c0, 0x478},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x0},
|
||||
{0x900c3, 0x1},
|
||||
{0x900c4, 0x8},
|
||||
{0x900c5, 0x8},
|
||||
{0x900c6, 0x4},
|
||||
{0x900c7, 0x8},
|
||||
{0x900c8, 0x8},
|
||||
{0x900c9, 0x7c8},
|
||||
{0x900ca, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x2b},
|
||||
};
|
||||
|
||||
static const struct pie pie_rdimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x40000, 0x10},
|
||||
{0x40020, 0x0},
|
||||
{0x40040, 0x0},
|
||||
{0x40060, 0x0},
|
||||
{0x40001, 0x70a},
|
||||
{0x40021, 0x7005},
|
||||
{0x40041, 0x0},
|
||||
{0x40061, 0x2001},
|
||||
{0x40002, 0x4010},
|
||||
{0x40022, 0x0},
|
||||
{0x40042, 0x0},
|
||||
{0x40062, 0x0},
|
||||
{0x90029, 0x10},
|
||||
{0x9002a, 0x400},
|
||||
{0x9002b, 0x16e},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x370},
|
||||
{0x9002e, 0x169},
|
||||
{0x9002f, 0x8},
|
||||
{0x90030, 0x7aa},
|
||||
{0x90031, 0x6a},
|
||||
{0x90032, 0x10},
|
||||
{0x90033, 0x7b2},
|
||||
{0x90034, 0x6a},
|
||||
{0x90035, 0x0},
|
||||
{0x90036, 0x48a},
|
||||
{0x90037, 0x6a},
|
||||
{0x90038, 0x9},
|
||||
{0x90039, 0x480},
|
||||
{0x9003a, 0x16a},
|
||||
{0x9003b, 0x4},
|
||||
{0x9003c, 0x790},
|
||||
{0x9003d, 0x16a},
|
||||
{0x9003e, 0xc},
|
||||
{0x9003f, 0x408},
|
||||
{0x90040, 0x169},
|
||||
{0x90041, 0xa},
|
||||
{0x90042, 0x0},
|
||||
{0x90043, 0x68},
|
||||
{0x90044, 0x0},
|
||||
{0x90045, 0x408},
|
||||
{0x90046, 0x169},
|
||||
{0x90047, 0x1},
|
||||
{0x90048, 0x480},
|
||||
{0x90049, 0x16a},
|
||||
{0x9004a, 0xb},
|
||||
{0x9004b, 0x480},
|
||||
{0x9004c, 0x109},
|
||||
{0x9004d, 0x8},
|
||||
{0x9004e, 0x448},
|
||||
{0x9004f, 0x139},
|
||||
{0x90050, 0x78},
|
||||
{0x90051, 0x8},
|
||||
{0x90052, 0x139},
|
||||
{0x90053, 0x2},
|
||||
{0x90054, 0x10},
|
||||
{0x90055, 0x139},
|
||||
{0x90056, 0xb},
|
||||
{0x90057, 0x7c0},
|
||||
{0x90058, 0x139},
|
||||
{0x90059, 0x44},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x159},
|
||||
{0x9005c, 0x14f},
|
||||
{0x9005d, 0x630},
|
||||
{0x9005e, 0x159},
|
||||
{0x9005f, 0x47},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x4f},
|
||||
{0x90063, 0x633},
|
||||
{0x90064, 0x179},
|
||||
{0x90065, 0x8},
|
||||
{0x90066, 0xe0},
|
||||
{0x90067, 0x109},
|
||||
{0x90068, 0x0},
|
||||
{0x90069, 0x7c8},
|
||||
{0x9006a, 0x109},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x1},
|
||||
{0x9006d, 0x8},
|
||||
{0x9006e, 0x0},
|
||||
{0x9006f, 0x45a},
|
||||
{0x90070, 0x9},
|
||||
{0x90071, 0x0},
|
||||
{0x90072, 0x448},
|
||||
{0x90073, 0x109},
|
||||
{0x90074, 0x40},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x179},
|
||||
{0x90077, 0x1},
|
||||
{0x90078, 0x618},
|
||||
{0x90079, 0x109},
|
||||
{0x9007a, 0x40c0},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x8},
|
||||
{0x9007e, 0x4},
|
||||
{0x9007f, 0x48},
|
||||
{0x90080, 0x4040},
|
||||
{0x90081, 0x633},
|
||||
{0x90082, 0x149},
|
||||
{0x90083, 0x0},
|
||||
{0x90084, 0x4},
|
||||
{0x90085, 0x48},
|
||||
{0x90086, 0x40},
|
||||
{0x90087, 0x633},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x10},
|
||||
{0x9008a, 0x4},
|
||||
{0x9008b, 0x18},
|
||||
{0x9008c, 0x0},
|
||||
{0x9008d, 0x4},
|
||||
{0x9008e, 0x78},
|
||||
{0x9008f, 0x549},
|
||||
{0x90090, 0x633},
|
||||
{0x90091, 0x159},
|
||||
{0x90092, 0xd49},
|
||||
{0x90093, 0x633},
|
||||
{0x90094, 0x159},
|
||||
{0x90095, 0x94a},
|
||||
{0x90096, 0x633},
|
||||
{0x90097, 0x159},
|
||||
{0x90098, 0x441},
|
||||
{0x90099, 0x633},
|
||||
{0x9009a, 0x149},
|
||||
{0x9009b, 0x42},
|
||||
{0x9009c, 0x633},
|
||||
{0x9009d, 0x149},
|
||||
{0x9009e, 0x1},
|
||||
{0x9009f, 0x633},
|
||||
{0x900a0, 0x149},
|
||||
{0x900a1, 0x0},
|
||||
{0x900a2, 0xe0},
|
||||
{0x900a3, 0x109},
|
||||
{0x900a4, 0xa},
|
||||
{0x900a5, 0x10},
|
||||
{0x900a6, 0x109},
|
||||
{0x900a7, 0x9},
|
||||
{0x900a8, 0x3c0},
|
||||
{0x900a9, 0x149},
|
||||
{0x900aa, 0x9},
|
||||
{0x900ab, 0x3c0},
|
||||
{0x900ac, 0x159},
|
||||
{0x900ad, 0x18},
|
||||
{0x900ae, 0x10},
|
||||
{0x900af, 0x109},
|
||||
{0x900b0, 0x0},
|
||||
{0x900b1, 0x3c0},
|
||||
{0x900b2, 0x109},
|
||||
{0x900b3, 0x18},
|
||||
{0x900b4, 0x4},
|
||||
{0x900b5, 0x48},
|
||||
{0x900b6, 0x18},
|
||||
{0x900b7, 0x4},
|
||||
{0x900b8, 0x58},
|
||||
{0x900b9, 0xb},
|
||||
{0x900ba, 0x10},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x1},
|
||||
{0x900bd, 0x10},
|
||||
{0x900be, 0x109},
|
||||
{0x900bf, 0x5},
|
||||
{0x900c0, 0x7c0},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x3},
|
||||
{0x900c3, 0x370},
|
||||
{0x900c4, 0x169},
|
||||
{0x900c5, 0x3},
|
||||
{0x900c6, 0x8},
|
||||
{0x900c7, 0x139},
|
||||
{0x900c8, 0x0},
|
||||
{0x900c9, 0x400},
|
||||
{0x900ca, 0x16e},
|
||||
{0x900cb, 0x8},
|
||||
{0x900cc, 0x478},
|
||||
{0x900cd, 0x109},
|
||||
{0x900ce, 0x0},
|
||||
{0x900cf, 0x8140},
|
||||
{0x900d0, 0x10c},
|
||||
{0x900d1, 0x10},
|
||||
{0x900d2, 0x8138},
|
||||
{0x900d3, 0x10c},
|
||||
{0x900d4, 0x8},
|
||||
{0x900d5, 0x7c8},
|
||||
{0x900d6, 0x101},
|
||||
{0x900d7, 0x7a},
|
||||
{0x900d8, 0x8},
|
||||
{0x900d9, 0x109},
|
||||
{0x900da, 0x8},
|
||||
{0x900db, 0x448},
|
||||
{0x900dc, 0x109},
|
||||
{0x900dd, 0xf},
|
||||
{0x900de, 0x7c0},
|
||||
{0x900df, 0x109},
|
||||
{0x900e0, 0x47},
|
||||
{0x900e1, 0x630},
|
||||
{0x900e2, 0x109},
|
||||
{0x900e3, 0x8},
|
||||
{0x900e4, 0x618},
|
||||
{0x900e5, 0x109},
|
||||
{0x900e6, 0x8},
|
||||
{0x900e7, 0xe0},
|
||||
{0x900e8, 0x109},
|
||||
{0x900e9, 0x0},
|
||||
{0x900ea, 0x8},
|
||||
{0x900eb, 0x109},
|
||||
{0x900ec, 0x0},
|
||||
{0x900ed, 0x7c8},
|
||||
{0x900ee, 0x109},
|
||||
{0x900ef, 0x8},
|
||||
{0x900f0, 0x8140},
|
||||
{0x900f1, 0x10c},
|
||||
{0x900f2, 0x0},
|
||||
{0x900f3, 0x478},
|
||||
{0x900f4, 0x109},
|
||||
{0x900f5, 0x0},
|
||||
{0x900f6, 0x1},
|
||||
{0x900f7, 0x8},
|
||||
{0x900f8, 0x8},
|
||||
{0x900f9, 0x4},
|
||||
{0x900fa, 0x8},
|
||||
{0x900fb, 0x8},
|
||||
{0x900fc, 0x7c8},
|
||||
{0x900fd, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x3a},
|
||||
};
|
||||
|
||||
static const struct pie pie_lrdimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x90029, 0xb},
|
||||
{0x9002a, 0x480},
|
||||
{0x9002b, 0x109},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x448},
|
||||
{0x9002e, 0x139},
|
||||
{0x9002f, 0x78},
|
||||
{0x90030, 0x8},
|
||||
{0x90031, 0x139},
|
||||
{0x90032, 0x2},
|
||||
{0x90033, 0x10},
|
||||
{0x90034, 0x139},
|
||||
{0x90035, 0xb},
|
||||
{0x90036, 0x7c0},
|
||||
{0x90037, 0x139},
|
||||
{0x90038, 0x44},
|
||||
{0x90039, 0x633},
|
||||
{0x9003a, 0x159},
|
||||
{0x9003b, 0x14f},
|
||||
{0x9003c, 0x630},
|
||||
{0x9003d, 0x159},
|
||||
{0x9003e, 0x47},
|
||||
{0x9003f, 0x633},
|
||||
{0x90040, 0x149},
|
||||
{0x90041, 0x4f},
|
||||
{0x90042, 0x633},
|
||||
{0x90043, 0x179},
|
||||
{0x90044, 0x8},
|
||||
{0x90045, 0xe0},
|
||||
{0x90046, 0x109},
|
||||
{0x90047, 0x0},
|
||||
{0x90048, 0x7c8},
|
||||
{0x90049, 0x109},
|
||||
{0x9004a, 0x0},
|
||||
{0x9004b, 0x1},
|
||||
{0x9004c, 0x8},
|
||||
{0x9004d, 0x0},
|
||||
{0x9004e, 0x45a},
|
||||
{0x9004f, 0x9},
|
||||
{0x90050, 0x0},
|
||||
{0x90051, 0x448},
|
||||
{0x90052, 0x109},
|
||||
{0x90053, 0x40},
|
||||
{0x90054, 0x633},
|
||||
{0x90055, 0x179},
|
||||
{0x90056, 0x1},
|
||||
{0x90057, 0x618},
|
||||
{0x90058, 0x109},
|
||||
{0x90059, 0x40c0},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x149},
|
||||
{0x9005c, 0x8},
|
||||
{0x9005d, 0x4},
|
||||
{0x9005e, 0x48},
|
||||
{0x9005f, 0x4040},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x0},
|
||||
{0x90063, 0x4},
|
||||
{0x90064, 0x48},
|
||||
{0x90065, 0x40},
|
||||
{0x90066, 0x633},
|
||||
{0x90067, 0x149},
|
||||
{0x90068, 0x10},
|
||||
{0x90069, 0x4},
|
||||
{0x9006a, 0x18},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x4},
|
||||
{0x9006d, 0x78},
|
||||
{0x9006e, 0x549},
|
||||
{0x9006f, 0x633},
|
||||
{0x90070, 0x159},
|
||||
{0x90071, 0xd49},
|
||||
{0x90072, 0x633},
|
||||
{0x90073, 0x159},
|
||||
{0x90074, 0x94a},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x159},
|
||||
{0x90077, 0x441},
|
||||
{0x90078, 0x633},
|
||||
{0x90079, 0x149},
|
||||
{0x9007a, 0x42},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x1},
|
||||
{0x9007e, 0x633},
|
||||
{0x9007f, 0x149},
|
||||
{0x90080, 0x0},
|
||||
{0x90081, 0xe0},
|
||||
{0x90082, 0x109},
|
||||
{0x90083, 0xa},
|
||||
{0x90084, 0x10},
|
||||
{0x90085, 0x109},
|
||||
{0x90086, 0x9},
|
||||
{0x90087, 0x3c0},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x9},
|
||||
{0x9008a, 0x3c0},
|
||||
{0x9008b, 0x159},
|
||||
{0x9008c, 0x18},
|
||||
{0x9008d, 0x10},
|
||||
{0x9008e, 0x109},
|
||||
{0x9008f, 0x0},
|
||||
{0x90090, 0x3c0},
|
||||
{0x90091, 0x109},
|
||||
{0x90092, 0x18},
|
||||
{0x90093, 0x4},
|
||||
{0x90094, 0x48},
|
||||
{0x90095, 0x18},
|
||||
{0x90096, 0x4},
|
||||
{0x90097, 0x58},
|
||||
{0x90098, 0xb},
|
||||
{0x90099, 0x10},
|
||||
{0x9009a, 0x109},
|
||||
{0x9009b, 0x1},
|
||||
{0x9009c, 0x10},
|
||||
{0x9009d, 0x109},
|
||||
{0x9009e, 0x5},
|
||||
{0x9009f, 0x7c0},
|
||||
{0x900a0, 0x109},
|
||||
{0x900a1, 0x3},
|
||||
{0x900a2, 0x8},
|
||||
{0x900a3, 0x139},
|
||||
{0x900a4, 0x0},
|
||||
{0x900a5, 0x400},
|
||||
{0x900a6, 0x16e},
|
||||
{0x900a7, 0x8},
|
||||
{0x900a8, 0x478},
|
||||
{0x900a9, 0x109},
|
||||
{0x900aa, 0x0},
|
||||
{0x900ab, 0x8140},
|
||||
{0x900ac, 0x10c},
|
||||
{0x900ad, 0x10},
|
||||
{0x900ae, 0x8138},
|
||||
{0x900af, 0x10c},
|
||||
{0x900b0, 0x8},
|
||||
{0x900b1, 0x7c8},
|
||||
{0x900b2, 0x101},
|
||||
{0x900b3, 0x7a},
|
||||
{0x900b4, 0x8},
|
||||
{0x900b5, 0x109},
|
||||
{0x900b6, 0x8},
|
||||
{0x900b7, 0x448},
|
||||
{0x900b8, 0x109},
|
||||
{0x900b9, 0xf},
|
||||
{0x900ba, 0x7c0},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x47},
|
||||
{0x900bd, 0x630},
|
||||
{0x900be, 0x109},
|
||||
{0x900bf, 0x8},
|
||||
{0x900c0, 0x618},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x8},
|
||||
{0x900c3, 0xe0},
|
||||
{0x900c4, 0x109},
|
||||
{0x900c5, 0x0},
|
||||
{0x900c6, 0x8},
|
||||
{0x900c7, 0x109},
|
||||
{0x900c8, 0x0},
|
||||
{0x900c9, 0x7c8},
|
||||
{0x900ca, 0x109},
|
||||
{0x900cb, 0x8},
|
||||
{0x900cc, 0x8140},
|
||||
{0x900cd, 0x10c},
|
||||
{0x900ce, 0x0},
|
||||
{0x900cf, 0x478},
|
||||
{0x900d0, 0x109},
|
||||
{0x900d1, 0x0},
|
||||
{0x900d2, 0x1},
|
||||
{0x900d3, 0x8},
|
||||
{0x900d4, 0x8},
|
||||
{0x900d5, 0x4},
|
||||
{0x900d6, 0x8},
|
||||
{0x900d7, 0x8},
|
||||
{0x900d8, 0x7c8},
|
||||
{0x900d9, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x2e},
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue