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Merge changes from topic "uniphier" into integration 

* changes:
  uniphier: make I/O register region configurable
  uniphier: make PSCI related base address configurable
  uniphier: make counter control base address configurable
  uniphier: make UART base address configurable
  uniphier: make pinmon base address configurable
  uniphier: make NAND controller base address configurable
  uniphier: make eMMC controller base address configurable
This commit is contained in:
Sandrine Bailleux 2020-02-14 08:26:05 +00:00 committed by TrustedFirmware Code Review
parent 25d583a858 eba319be6c
commit b3add9cbf1
11 changed files with 209 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
View File

@ -4,16 +4,25 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <platform_def.h>
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <plat/common/platform.h>
#include "../uniphier.h"
static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
void tsp_early_platform_setup(void)
{
uniphier_console_setup();
uniphier_soc = uniphier_get_soc_id();
if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
plat_error_handler(-ENOTSUP);
uniphier_console_setup(uniphier_soc);
}
void tsp_platform_setup(void)
@ -22,6 +31,6 @@ void tsp_platform_setup(void)
void tsp_plat_arch_setup(void)
{
uniphier_mmap_setup();
uniphier_mmap_setup(uniphier_soc);
enable_mmu_el1(0);
}

12
plat/socionext/uniphier/uniphier.h
View File

@ -35,11 +35,13 @@ unsigned int uniphier_get_boot_master(unsigned int soc);
#define UNIPHIER_BOOT_MASTER_SCP 1
#define UNIPHIER_BOOT_MASTER_EXT 2
void uniphier_console_setup(void);
void uniphier_console_setup(unsigned int soc);
struct io_block_dev_spec;
int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec);
int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec);
int uniphier_emmc_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec);
int uniphier_nand_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec);
int uniphier_usb_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec);
@ -55,7 +57,7 @@ void uniphier_scp_open_com(void);
void uniphier_scp_system_off(void);
void uniphier_scp_system_reset(void);
void uniphier_mmap_setup(void);
void uniphier_mmap_setup(unsigned int soc);
void uniphier_cci_init(unsigned int soc);
void uniphier_cci_enable(void);
@ -67,6 +69,8 @@ void uniphier_gic_cpuif_enable(void);
void uniphier_gic_cpuif_disable(void);
void uniphier_gic_pcpu_init(void);
void uniphier_psci_init(unsigned int soc);
unsigned int uniphier_calc_core_pos(u_register_t mpidr);
#endif /* UNIPHIER_H */

20
plat/socionext/uniphier/uniphier_bl2_setup.c
View File

@ -25,39 +25,37 @@
#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL
static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
static int uniphier_bl2_kick_scp;
void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
u_register_t x2, u_register_t x3)
{
uniphier_console_setup();
uniphier_soc = uniphier_get_soc_id();
if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
plat_error_handler(-ENOTSUP);
uniphier_console_setup(uniphier_soc);
}
void bl2_el3_plat_arch_setup(void)
{
unsigned int soc;
int skip_scp = 0;
int ret;
uniphier_mmap_setup();
uniphier_mmap_setup(uniphier_soc);
enable_mmu_el3(0);
/* add relocation offset (run-time-address - link-address) */
uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
soc = uniphier_get_soc_id();
if (soc == UNIPHIER_SOC_UNKNOWN) {
ERROR("unsupported SoC\n");
plat_error_handler(-ENOTSUP);
}
ret = uniphier_io_setup(soc, uniphier_mem_base);
ret = uniphier_io_setup(uniphier_soc, uniphier_mem_base);
if (ret) {
ERROR("failed to setup io devices\n");
plat_error_handler(ret);
}
switch (uniphier_get_boot_master(soc)) {
switch (uniphier_get_boot_master(uniphier_soc)) {
case UNIPHIER_BOOT_MASTER_THIS:
INFO("Booting from this SoC\n");
skip_scp = 1;

35
plat/socionext/uniphier/uniphier_bl31_setup.c
View File

@ -21,6 +21,7 @@
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
@ -37,7 +38,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
uniphier_console_setup();
uniphier_soc = uniphier_get_soc_id();
if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
plat_error_handler(-ENOTSUP);
uniphier_console_setup(uniphier_soc);
while (bl_params) {
if (bl_params->image_id == BL32_IMAGE_ID)
@ -53,32 +58,34 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic();
}
#define UNIPHIER_SYS_CNTCTL_BASE 0x60E00000
static const uintptr_t uniphier_cntctl_base[] = {
[UNIPHIER_SOC_LD11] = 0x60e00000,
[UNIPHIER_SOC_LD20] = 0x60e00000,
[UNIPHIER_SOC_PXS3] = 0x60e00000,
};
void bl31_platform_setup(void)
{
unsigned int soc;
uintptr_t cntctl_base;
soc = uniphier_get_soc_id();
if (soc == UNIPHIER_SOC_UNKNOWN) {
ERROR("unsupported SoC\n");
plat_error_handler(-ENOTSUP);
}
uniphier_cci_init(soc);
uniphier_cci_init(uniphier_soc);
uniphier_cci_enable();
/* Initialize the GIC driver, cpu and distributor interfaces */
uniphier_gic_driver_init(soc);
uniphier_gic_driver_init(uniphier_soc);
uniphier_gic_init();
assert(uniphier_soc < ARRAY_SIZE(uniphier_cntctl_base));
cntctl_base = uniphier_cntctl_base[uniphier_soc];
/* Enable and initialize the System level generic timer */
mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0U) | CNTCR_EN);
mmio_write_32(cntctl_base + CNTCR_OFF, CNTCR_FCREQ(0U) | CNTCR_EN);
uniphier_psci_init(uniphier_soc);
}
void bl31_plat_arch_setup(void)
{
uniphier_mmap_setup();
uniphier_mmap_setup(uniphier_soc);
enable_mmu_el3(0);
}

26
plat/socionext/uniphier/uniphier_boot_device.c
View File

@ -13,8 +13,14 @@
#include "uniphier.h"
#define UNIPHIER_PINMON0 0x5f900100
#define UNIPHIER_PINMON2 0x5f900108
#define UNIPHIER_PINMON0 0x0
#define UNIPHIER_PINMON2 0x8
static const uintptr_t uniphier_pinmon_base[] = {
[UNIPHIER_SOC_LD11] = 0x5f900100,
[UNIPHIER_SOC_LD20] = 0x5f900100,
[UNIPHIER_SOC_PXS3] = 0x5f900100,
};
static bool uniphier_ld11_is_usb_boot(uint32_t pinmon)
{
@ -28,7 +34,8 @@ static bool uniphier_ld20_is_usb_boot(uint32_t pinmon)
static bool uniphier_pxs3_is_usb_boot(uint32_t pinmon)
{
uint32_t pinmon2 = mmio_read_32(UNIPHIER_PINMON2);
uintptr_t pinmon_base = uniphier_pinmon_base[UNIPHIER_SOC_PXS3];
uint32_t pinmon2 = mmio_read_32(pinmon_base + UNIPHIER_PINMON2);
return !!(pinmon2 & BIT(31));
}
@ -133,12 +140,16 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
unsigned int uniphier_get_boot_device(unsigned int soc)
{
const struct uniphier_boot_device_info *info;
uintptr_t pinmon_base;
uint32_t pinmon;
assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
info = &uniphier_boot_device_info[soc];
pinmon = mmio_read_32(UNIPHIER_PINMON0);
assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
pinmon_base = uniphier_pinmon_base[soc];
pinmon = mmio_read_32(pinmon_base + UNIPHIER_PINMON0);
if (info->have_boot_swap && !(pinmon & BIT(29)))
return UNIPHIER_BOOT_DEVICE_NOR;
@ -163,7 +174,12 @@ unsigned int uniphier_get_boot_master(unsigned int soc)
assert(soc < ARRAY_SIZE(uniphier_have_onchip_scp));
if (uniphier_have_onchip_scp[soc]) {
if (mmio_read_32(UNIPHIER_PINMON0) & BIT(27))
uintptr_t pinmon_base;
assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
pinmon_base = uniphier_pinmon_base[soc];
if (mmio_read_32(pinmon_base + UNIPHIER_PINMON0) & BIT(27))
return UNIPHIER_BOOT_MASTER_THIS;
else
return UNIPHIER_BOOT_MASTER_SCP;

27
plat/socionext/uniphier/uniphier_console_setup.c
View File

@ -1,9 +1,11 @@
/*
* Copyright (c) 2019, Socionext Inc. All rights reserved.
* Copyright (c) 2019-2020, Socionext Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <drivers/console.h>
#include <errno.h>
#include <lib/mmio.h>
@ -12,9 +14,8 @@
#include "uniphier.h"
#include "uniphier_console.h"
#define UNIPHIER_UART_BASE 0x54006800
#define UNIPHIER_UART_END 0x54006c00
#define UNIPHIER_UART_OFFSET 0x100
#define UNIPHIER_UART_NR_PORTS 4
struct uniphier_console {
struct console console;
@ -40,16 +41,26 @@ static struct uniphier_console uniphier_console = {
},
};
static const uintptr_t uniphier_uart_base[] = {
[UNIPHIER_SOC_LD11] = 0x54006800,
[UNIPHIER_SOC_LD20] = 0x54006800,
[UNIPHIER_SOC_PXS3] = 0x54006800,
};
/*
* There are 4 UART ports available on this platform. By default, we want to
* use the same one as used in the previous firmware stage.
*/
static uintptr_t uniphier_console_get_base(void)
static uintptr_t uniphier_console_get_base(unsigned int soc)
{
uintptr_t base = UNIPHIER_UART_BASE;
uintptr_t base, end;
uint32_t div;
while (base < UNIPHIER_UART_END) {
assert(soc < ARRAY_SIZE(uniphier_uart_base));
base = uniphier_uart_base[soc];
end = base + UNIPHIER_UART_OFFSET * UNIPHIER_UART_NR_PORTS;
while (base < end) {
div = mmio_read_32(base + UNIPHIER_UART_DLR);
if (div)
return base;
@ -66,11 +77,11 @@ static void uniphier_console_init(uintptr_t base)
UNIPHIER_UART_LCR_WLEN8 << 8);
}
void uniphier_console_setup(void)
void uniphier_console_setup(unsigned int soc)
{
uintptr_t base;
base = uniphier_console_get_base();
base = uniphier_console_get_base(soc);
if (!base)
plat_error_handler(-EINVAL);

35
plat/socionext/uniphier/uniphier_emmc.c
View File

@ -87,7 +87,12 @@ struct uniphier_mmc_cmd {
unsigned int is_data;
};
static bool uniphier_emmc_block_addressing;
struct uniphier_emmc_host {
uintptr_t base;
bool is_block_addressing;
};
static struct uniphier_emmc_host uniphier_emmc_host;
static int uniphier_emmc_send_cmd(uintptr_t host_base,
struct uniphier_mmc_cmd *cmd)
@ -214,15 +219,15 @@ static int uniphier_emmc_load_image(uintptr_t host_base,
static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size)
{
uintptr_t host_base = 0x5a000200;
int ret;
inv_dcache_range(buf, size);
if (!uniphier_emmc_block_addressing)
if (!uniphier_emmc_host.is_block_addressing)
lba *= 512;
ret = uniphier_emmc_load_image(host_base, lba, buf, size / 512);
ret = uniphier_emmc_load_image(uniphier_emmc_host.base,
lba, buf, size / 512);
inv_dcache_range(buf, size);
@ -236,10 +241,10 @@ static struct io_block_dev_spec uniphier_emmc_dev_spec = {
.block_size = 512,
};
static int uniphier_emmc_hw_init(void)
static int uniphier_emmc_hw_init(struct uniphier_emmc_host *host)
{
uintptr_t host_base = 0x5a000200;
struct uniphier_mmc_cmd cmd = {0};
uintptr_t host_base = uniphier_emmc_host.base;
int ret;
/*
@ -258,7 +263,7 @@ static int uniphier_emmc_hw_init(void)
;
ret = uniphier_emmc_check_device_size(host_base,
&uniphier_emmc_block_addressing);
&uniphier_emmc_host.is_block_addressing);
if (ret)
return ret;
@ -277,11 +282,23 @@ static int uniphier_emmc_hw_init(void)
return 0;
}
int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec)
static const uintptr_t uniphier_emmc_base[] = {
[UNIPHIER_SOC_LD11] = 0x5a000200,
[UNIPHIER_SOC_LD20] = 0x5a000200,
[UNIPHIER_SOC_PXS3] = 0x5a000200,
};
int uniphier_emmc_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec)
{
int ret;
ret = uniphier_emmc_hw_init();
assert(soc < ARRAY_SIZE(uniphier_emmc_base));
uniphier_emmc_host.base = uniphier_emmc_base[soc];
if (uniphier_emmc_host.base == 0UL)
return -ENOTSUP;
ret = uniphier_emmc_hw_init(&uniphier_emmc_host);
if (ret)
return ret;

8
plat/socionext/uniphier/uniphier_io_storage.c
View File

@ -249,24 +249,24 @@ static int uniphier_io_fip_setup(void)
return io_dev_open(uniphier_fip_dev_con, 0, &uniphier_fip_dev_handle);
}
static int uniphier_io_emmc_setup(unsigned int soc_id, size_t buffer_offset)
static int uniphier_io_emmc_setup(unsigned int soc, size_t buffer_offset)
{
struct io_block_dev_spec *block_dev_spec;
int ret;
ret = uniphier_emmc_init(&block_dev_spec);
ret = uniphier_emmc_init(soc, &block_dev_spec);
if (ret)
return ret;
return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset);
}
static int uniphier_io_nand_setup(unsigned int soc_id, size_t buffer_offset)
static int uniphier_io_nand_setup(unsigned int soc, size_t buffer_offset)
{
struct io_block_dev_spec *block_dev_spec;
int ret;
ret = uniphier_nand_init(&block_dev_spec);
ret = uniphier_nand_init(soc, &block_dev_spec);
if (ret)
return ret;

18
plat/socionext/uniphier/uniphier_nand.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <stdint.h>
#include <platform_def.h>
@ -237,8 +238,7 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand)
for (i = 0; i < ARRAY_SIZE(nand->bbt); i++)
nand->bbt[i] = UNIPHIER_NAND_BBT_UNKNOWN;
nand->host_base = 0x68000000;
nand->reg_base = 0x68100000;
nand->reg_base = nand->host_base + 0x100000;
nand->pages_per_block =
mmio_read_32(nand->reg_base + DENALI_PAGES_PER_BLOCK);
@ -255,10 +255,22 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand)
return 0;
}
int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec)
static const uintptr_t uniphier_nand_base[] = {
[UNIPHIER_SOC_LD11] = 0x68000000,
[UNIPHIER_SOC_LD20] = 0x68000000,
[UNIPHIER_SOC_PXS3] = 0x68000000,
};
int uniphier_nand_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec)
{
int ret;
assert(soc < ARRAY_SIZE(uniphier_nand_base));
uniphier_nand.host_base = uniphier_nand_base[soc];
if (!uniphier_nand.host_base)
return -ENOTSUP;
ret = uniphier_nand_hw_init(&uniphier_nand);
if (ret)
return ret;

68
plat/socionext/uniphier/uniphier_psci.c
View File

@ -1,9 +1,11 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <errno.h>
@ -12,15 +14,18 @@
#include "uniphier.h"
#define UNIPHIER_ROM_RSV0 0x59801200
#define UNIPHIER_ROM_RSV0 0x0
#define UNIPHIER_SLFRSTSEL 0x61843010
#define UNIPHIER_SLFRSTSEL 0x10
#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0)
#define UNIPHIER_SLFRSTCTL 0x61843014
#define UNIPHIER_SLFRSTCTL 0x14
#define UNIPHIER_SLFRSTCTL_RST BIT(0)
#define MPIDR_AFFINITY_INVALID ((u_register_t)-1)
static uintptr_t uniphier_rom_rsv_base;
static uintptr_t uniphier_slfrst_base;
uintptr_t uniphier_sec_entrypoint;
void uniphier_warmboot_entrypoint(void);
@ -34,7 +39,7 @@ static int uniphier_psci_pwr_domain_on(u_register_t mpidr)
flush_dcache_range((uint64_t)&uniphier_holding_pen_release,
sizeof(uniphier_holding_pen_release));
mmio_write_64(UNIPHIER_ROM_RSV0,
mmio_write_64(uniphier_rom_rsv_base + UNIPHIER_ROM_RSV0,
(uint64_t)&uniphier_warmboot_entrypoint);
sev();
@ -71,8 +76,10 @@ static void __dead2 uniphier_psci_pwr_domain_pwr_down_wfi(
static void uniphier_self_system_reset(void)
{
mmio_clrbits_32(UNIPHIER_SLFRSTSEL, UNIPHIER_SLFRSTSEL_MASK);
mmio_setbits_32(UNIPHIER_SLFRSTCTL, UNIPHIER_SLFRSTCTL_RST);
mmio_clrbits_32(uniphier_slfrst_base + UNIPHIER_SLFRSTSEL,
UNIPHIER_SLFRSTSEL_MASK);
mmio_setbits_32(uniphier_slfrst_base + UNIPHIER_SLFRSTCTL,
UNIPHIER_SLFRSTCTL_RST);
}
static void __dead2 uniphier_psci_system_off(void)
@ -114,13 +121,40 @@ static const struct plat_psci_ops uniphier_psci_ops = {
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **psci_ops)
{
unsigned int soc;
uniphier_sec_entrypoint = sec_entrypoint;
flush_dcache_range((uint64_t)&uniphier_sec_entrypoint,
sizeof(uniphier_sec_entrypoint));
soc = uniphier_get_soc_id();
if (soc == UNIPHIER_SOC_UNKNOWN) {
ERROR("unsupported SoC\n");
return -ENOTSUP;
}
*psci_ops = &uniphier_psci_ops;
return 0;
}
struct uniphier_psci_ctrl_base {
uintptr_t rom_rsv_base;
uintptr_t slfrst_base;
};
static const struct uniphier_psci_ctrl_base uniphier_psci_ctrl_base[] = {
[UNIPHIER_SOC_LD11] = {
.rom_rsv_base = 0x59801200,
.slfrst_base = 0x61843000,
},
[UNIPHIER_SOC_LD20] = {
.rom_rsv_base = 0x59801200,
.slfrst_base = 0x61843000,
},
[UNIPHIER_SOC_PXS3] = {
.rom_rsv_base = 0x59801200,
.slfrst_base = 0x61843000,
},
};
void uniphier_psci_init(unsigned int soc)
{
assert(soc < ARRAY_SIZE(uniphier_psci_ctrl_base));
uniphier_rom_rsv_base = uniphier_psci_ctrl_base[soc].rom_rsv_base;
uniphier_slfrst_base = uniphier_psci_ctrl_base[soc].slfrst_base;
if (uniphier_get_boot_master(soc) == UNIPHIER_BOOT_MASTER_SCP) {
uniphier_psci_scp_mode = uniphier_scp_is_running();
@ -130,12 +164,4 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
if (uniphier_psci_scp_mode)
uniphier_scp_open_com();
}
uniphier_sec_entrypoint = sec_entrypoint;
flush_dcache_range((uint64_t)&uniphier_sec_entrypoint,
sizeof(uniphier_sec_entrypoint));
*psci_ops = &uniphier_psci_ops;
return 0;
}

33
plat/socionext/uniphier/uniphier_xlat_setup.c
View File

@ -4,15 +4,36 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <common/debug.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#define UNIPHIER_REG_REGION_BASE 0x50000000ULL
#define UNIPHIER_REG_REGION_SIZE 0x20000000ULL
#include "uniphier.h"
void uniphier_mmap_setup(void)
struct uniphier_reg_region {
uintptr_t base;
size_t size;
};
static const struct uniphier_reg_region uniphier_reg_region[] = {
[UNIPHIER_SOC_LD11] = {
.base = 0x50000000UL,
.size = 0x20000000UL,
},
[UNIPHIER_SOC_LD20] = {
.base = 0x50000000UL,
.size = 0x20000000UL,
},
[UNIPHIER_SOC_PXS3] = {
.base = 0x50000000UL,
.size = 0x20000000UL,
},
};
void uniphier_mmap_setup(unsigned int soc)
{
VERBOSE("Trusted RAM seen by this BL image: %p - %p\n",
(void *)BL_CODE_BASE, (void *)BL_END);
@ -35,8 +56,10 @@ void uniphier_mmap_setup(void)
MT_DEVICE | MT_RW | MT_SECURE);
/* register region */
mmap_add_region(UNIPHIER_REG_REGION_BASE, UNIPHIER_REG_REGION_BASE,
UNIPHIER_REG_REGION_SIZE,
assert(soc < ARRAY_SIZE(uniphier_reg_region));
mmap_add_region(uniphier_reg_region[soc].base,
uniphier_reg_region[soc].base,
uniphier_reg_region[soc].size,
MT_DEVICE | MT_RW | MT_SECURE);
init_xlat_tables();