From b3c431f35b45bdd284fd041785bdf28b32049c1a Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 24 Feb 2020 10:39:31 +0000 Subject: [PATCH] FVP: Fix incorrect GIC mapping This patch fixes incorrect setting for DEVICE1_SIZE for FVP platforms with more than 8 PEs. The current value of 0x200000 supports only 8 PEs and causes exception for FVP platforms with the greater number of PEs, e.g. FVP_Base_Cortex_A65AEx8 with 16 PEs in one cluster. Change-Id: Ie6391509fe6eeafb8ba779303636cd762e7d21b2 Signed-off-by: Alexei Fedorov --- plat/arm/board/fvp/fvp_def.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 347ba2e1e..909b68717 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -52,8 +52,10 @@ #define DEVICE1_BASE UL(0x2e000000) #define DEVICE1_SIZE UL(0x1A00000) #else -#define DEVICE1_BASE UL(0x2f000000) -#define DEVICE1_SIZE UL(0x200000) +/* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */ +#define DEVICE1_BASE BASE_GICD_BASE +#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \ + (PLATFORM_CORE_COUNT * 0x20000)) #define NSRAM_BASE UL(0x2e000000) #define NSRAM_SIZE UL(0x10000) #endif @@ -110,7 +112,7 @@ #define FVP_SP810_CTRL_TIM3_OV BIT_32(22) /******************************************************************************* - * GIC-400 & interrupt handling related constants + * GIC & interrupt handling related constants ******************************************************************************/ /* VE compatible GIC memory map */ #define VE_GICD_BASE UL(0x2c001000) @@ -128,7 +130,6 @@ #define FVP_IRQ_TZ_WDOG 56 #define FVP_IRQ_SEC_SYS_TIMER 57 - /******************************************************************************* * TrustZone address space controller related constants ******************************************************************************/