zynqmp: pm: Add LPD WDT clock to the pm_clock structure
This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -330,6 +330,7 @@
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#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
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#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
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#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
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#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
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/* Global general storage register base address */
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#define GGS_BASEADDR (0xFFD80030U)
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@ -2198,6 +2198,18 @@ static struct pm_clock clocks[] = {
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.nodes = &can1_nodes,
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.num_nodes = ARRAY_SIZE(can1_nodes),
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},
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[CLK_LPD_WDT] = {
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.name = "lpd_wdt",
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.control_reg = IOU_SLCR_WDT_CLK_SEL,
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.status_reg = 0,
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.parents = &((int32_t []) {
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CLK_LPD_LSBUS,
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EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
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CLK_NA_PARENT
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}),
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.nodes = &wdt_nodes,
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.num_nodes = ARRAY_SIZE(wdt_nodes),
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},
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};
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static struct pm_ext_clock ext_clocks[] = {
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@ -2343,7 +2355,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB,
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CLK_TOPSW_LSBUS,
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CLK_GTGREF0_REF,
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CLK_LPD_SWITCH,
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CLK_LPD_LSBUS,
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CLK_CPU_R5,
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CLK_CPU_R5_CORE,
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CLK_CSU_SPB,
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@ -169,6 +169,7 @@ enum clock_id {
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CLK_GEM1_REF_UNGATED,
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CLK_GEM2_REF_UNGATED,
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CLK_GEM3_REF_UNGATED,
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CLK_LPD_WDT,
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END_OF_OUTPUT_CLKS,
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};
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