Merge pull request #1655 from deepan02/deepak-arm/introduce-n1sdp
plat/arm: Introduce the N1SDP.
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
b3f7c42d37
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_ares.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.globl plat_arm_calc_core_pos
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.globl plat_reset_handler
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Helper function to calculate the core position.
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* (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) +
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* (CPUId * N1SDP_MAX_PE_PER_CPU) +
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* ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) *
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* N1SDP_MAX_PE_PER_CPU) + ThreadId
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* ------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov x3, x0
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/*
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* The MT bit in MPIDR is always set for n1sdp and the
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* affinity level 0 corresponds to thread affinity level.
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*/
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x5, #N1SDP_MAX_PE_PER_CPU
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madd x0, x1, x5, x0
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ret
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endfunc plat_arm_calc_core_pos
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/* -----------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Determine the CPU MIDR and disable power down bit for
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* that CPU.
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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jump_if_cpu_midr CORTEX_ARES_MIDR, ARES
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ret
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/* -----------------------------------------------------
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* Disable CPU power down bit in power control register
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* -----------------------------------------------------
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*/
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ARES:
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mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1
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bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
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msr CORTEX_ARES_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc plat_reset_handler
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_MACROS_S__
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#define __PLAT_MACROS_S__
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#include <css_macros.S>
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant platform registers
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* whenever an unhandled exception is taken in
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* BL31.
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*
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* There are currently no platform specific regs
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* to print.
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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.endm
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#endif /* __PLAT_MACROS_S__ */
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arm_def.h>
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#include <board_css_def.h>
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#include <css_def.h>
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#if CSS_USE_SCMI_SDS_DRIVER
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#define N1SDP_SCMI_PAYLOAD_BASE 0x45400000
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#else
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
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#endif
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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#define PLAT_ARM_MAX_BL31_SIZE 0X20000
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/*******************************************************************************
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* N1SDP topology related constants
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******************************************************************************/
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#define N1SDP_MAX_CPUS_PER_CLUSTER 2
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define N1SDP_MAX_PE_PER_CPU 1
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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N1SDP_MAX_CPUS_PER_CLUSTER * \
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N1SDP_MAX_PE_PER_CPU)
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#define PLAT_ARM_MMAP_ENTRIES 3
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#define MAX_XLAT_TABLES 4
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#define PLATFORM_STACK_SIZE 0x400
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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CSS_IRQ_MHU
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#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define N1SDP_DEVICE_BASE (0x20000000)
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#define N1SDP_DEVICE_SIZE (0x20000000)
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#endif /* __PLATFORM_DEF_H__ */
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "../../css/drivers/scmi/scmi.h"
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#include "../../css/drivers/mhu/css_mhu_doorbell.h"
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#include <platform_def.h>
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static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
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.scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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};
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scmi_channel_plat_info_t *plat_css_get_scmi_info()
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{
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return &n1sdp_scmi_plat_info;
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}
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* For N1SDP which support FCM (with automatic interconnect enter/exit),
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* we should not do anything in these interface functions.
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* They are used to override the weak functions in cci drivers.
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*/
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/******************************************************************************
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* Helper function to initialize ARM interconnect driver.
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*****************************************************************************/
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void plat_arm_interconnect_init(void)
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{
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}
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/******************************************************************************
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* Helper function to place current master into coherency
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*****************************************************************************/
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void plat_arm_interconnect_enter_coherency(void)
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{
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}
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/******************************************************************************
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* Helper function to remove current master from coherency
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*****************************************************************************/
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void plat_arm_interconnect_exit_coherency(void)
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{
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}
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_def.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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/*
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* Table of regions to map using the MMU.
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* Replace or extend the below regions as required
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*/
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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N1SDP_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* TZC programming is currently not done.
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*/
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void plat_arm_security_setup(void)
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{
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}
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat_arm.h>
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/* Topology */
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typedef struct n1sdp_topology {
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const unsigned char *power_tree;
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unsigned int plat_cluster_core_count;
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} n1sdp_topology_t;
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/*
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* The power domain tree descriptor. The cluster power domains are
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* arranged so that when the PSCI generic code creates the power domain tree,
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* the indices of the CPU power domain nodes it allocates match the linear
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* indices returned by plat_core_pos_by_mpidr().
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*/
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const unsigned char n1sdp_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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N1SDP_MAX_CPUS_PER_CLUSTER,
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N1SDP_MAX_CPUS_PER_CLUSTER
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};
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/* Topology configuration for n1sdp */
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const n1sdp_topology_t n1sdp_topology = {
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.power_tree = n1sdp_pd_tree_desc,
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.plat_cluster_core_count = N1SDP_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return n1sdp_topology.power_tree;
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}
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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******************************************************************************/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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{
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return n1sdp_topology.plat_cluster_core_count;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
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0, 1, 2, 3};
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#
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# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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N1SDP_BASE := plat/arm/board/n1sdp
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INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c
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PLAT_INCLUDES := -I${N1SDP_BASE}/include
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N1SDP_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S
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N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v3/gicv3_main.c \
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drivers/arm/gic/v3/gicv3_helpers.c \
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plat/common/plat_gicv3.c \
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plat/arm/common/arm_gicv3.c \
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drivers/arm/gic/v3/gic600.c
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PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
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${N1SDP_BASE}/aarch64/n1sdp_helper.S
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BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
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${INTERCONNECT_SOURCES} \
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${N1SDP_GIC_SOURCES} \
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${N1SDP_BASE}/n1sdp_bl31_setup.c \
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${N1SDP_BASE}/n1sdp_topology.c \
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${N1SDP_BASE}/n1sdp_security.c
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# TF-A not required to load the SCP Images
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override CSS_LOAD_SCP_IMAGES := 0
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# BL1/BL2 Image not a part of the capsule Image for n1sdp
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override NEED_BL1 := no
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override NEED_BL2 := no
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override NEED_BL2U := no
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#TFA for n1sdp starts from BL31
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override RESET_TO_BL31 := 1
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# 32 bit mode not supported
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override CTX_INCLUDE_AARCH32_REGS := 0
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override ARM_PLAT_MT := 1
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# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
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# SCP during power management operations and for SCP RAM Firmware transfer.
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CSS_USE_SCMI_SDS_DRIVER := 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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USE_COHERENT_MEM := 0
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include plat/arm/common/arm_common.mk
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include plat/arm/css/common/css_common.mk
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include plat/arm/soc/common/soc_css.mk
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include plat/arm/board/common/board_common.mk
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