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Tegra186: reset power state info during CPU_ON 

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-04-09 00:40:45 -07:00
parent abd3a91d6f
commit b46ac6dcc5
1 changed files with 12 additions and 0 deletions
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12
plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
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@ -246,6 +246,18 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
cpu_context_t *ctx = cm_get_context(NON_SECURE);
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
/*
* Reset power state info for CPUs when onlining, we set deepest power
* when offlining a core but that may not be requested by non-secure
* sw which controls idle states. It will re-init this info from
* non-secure software when the core come online.
*/
write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1,
0, 0);
/*
* Check if we are exiting from deep sleep and restore SE
* context if we are.