andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

docs(fvp): update loading addresses of HW_CONFIG 

As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load region of HW_CONFIG in FVP Arm
platform.

Additionally, added a note on how FW_CONFIG address gets
passed from BL2 to BL31/SP_MIN.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14620

Change-Id: I37e02ff4f433c87bccbe67c7df5ecde3017668b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit is contained in:
Manish V Badarkhe 2022-04-12 21:11:56 +01:00
parent b80e751d99
commit b4a878367f
1 changed files with 31 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
docs/design/firmware-design.rst
View File

@ -131,6 +131,9 @@ convention:
- For other BL3x images, if the firmware configuration file is loaded by
BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
then its address is passed in ``arg1``.
- In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to
BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved
from FW_CONFIG device tree.
BL1
~~~
@ -1757,12 +1760,20 @@ BL image during boot.
DRAM
0xffffffff +----------+
: :
|----------|
0x82100000 |----------|
|HW_CONFIG |
0x83000000 |----------| (non-secure)
0x82000000 |----------| (non-secure)
| |
0x80000000 +----------+
Trusted DRAM
0x08000000 +----------+
|HW_CONFIG |
0x07f00000 |----------|
: :
| |
0x06000000 +----------+
Trusted SRAM
0x04040000 +----------+ loaded by BL2 +----------------+
| BL1 (rw) | <<<<<<<<<<<<< | |
@ -1790,15 +1801,18 @@ BL image during boot.
DRAM
0xffffffff +--------------+
: :
|--------------|
0x82100000 |--------------|
| HW_CONFIG |
0x83000000 |--------------| (non-secure)
0x82000000 |--------------| (non-secure)
| |
0x80000000 +--------------+
Trusted DRAM
Trusted DRAM
0x08000000 +--------------+
| BL32 |
| HW_CONFIG |
0x07f00000 |--------------|
: :
| BL32 |
0x06000000 +--------------+
Trusted SRAM
@ -1829,12 +1843,20 @@ BL image during boot.
| BL32 | (secure)
0xff000000 +----------+
| |
|----------|
0x82100000 |----------|
|HW_CONFIG |
0x83000000 |----------| (non-secure)
0x82000000 |----------| (non-secure)
| |
0x80000000 +----------+
Trusted DRAM
0x08000000 +----------+
|HW_CONFIG |
0x7f000000 |----------|
: :
| |
0x06000000 +----------+
Trusted SRAM
0x04040000 +----------+ loaded by BL2 +----------------+
| BL1 (rw) | <<<<<<<<<<<<< | |
@ -2729,7 +2751,7 @@ kernel at boot time. These can be found in the ``fdts`` directory.
--------------
*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMCCC: https://developer.arm.com/docs/den0028/latest