refactor(amu)!: privatize unused AMU APIs
This change reduces the exposed surface area of the AMU API in order to simplify the refactoring work in following patches. The functions and definitions privatized by this change are not used by other parts of the code-base today. BREAKING CHANGE: The public AMU API has been reduced to enablement only to facilitate refactoring work. These APIs were not previously used. Change-Id: Ibf6174fb5b3949de3c4ba6847cce47d82a6bd08c Signed-off-by: Chris Kay <chris.kay@arm.com>
This commit is contained in:
Chris Kay
parent
6c8dda19e5
commit
b4b726ea86
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@ -8,103 +8,12 @@
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#define AMU_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <lib/cassert.h>
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#include <lib/utils_def.h>
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#include <context.h>
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#include <platform_def.h>
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/* All group 0 counters */
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#define AMU_GROUP0_COUNTERS_MASK U(0xf)
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#define AMU_GROUP0_NR_COUNTERS U(4)
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#define AMU_GROUP1_COUNTERS_MASK U(0)
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/* Calculate number of group 1 counters */
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#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15))
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#define AMU_GROUP1_NR_COUNTERS 16U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14))
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#define AMU_GROUP1_NR_COUNTERS 15U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13))
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#define AMU_GROUP1_NR_COUNTERS 14U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12))
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#define AMU_GROUP1_NR_COUNTERS 13U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11))
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#define AMU_GROUP1_NR_COUNTERS 12U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10))
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#define AMU_GROUP1_NR_COUNTERS 11U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9))
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#define AMU_GROUP1_NR_COUNTERS 10U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8))
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#define AMU_GROUP1_NR_COUNTERS 9U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7))
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#define AMU_GROUP1_NR_COUNTERS 8U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6))
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#define AMU_GROUP1_NR_COUNTERS 7U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5))
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#define AMU_GROUP1_NR_COUNTERS 6U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4))
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#define AMU_GROUP1_NR_COUNTERS 5U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3))
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#define AMU_GROUP1_NR_COUNTERS 4U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2))
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#define AMU_GROUP1_NR_COUNTERS 3U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1))
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#define AMU_GROUP1_NR_COUNTERS 2U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0))
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#define AMU_GROUP1_NR_COUNTERS 1U
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#else
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#define AMU_GROUP1_NR_COUNTERS 0U
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#endif
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CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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#if __aarch64__
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/* Architected event counter 1 does not have an offset register. */
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uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1];
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#endif
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#if AMU_GROUP1_NR_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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#if __aarch64__
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uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS];
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#endif
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#endif
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};
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unsigned int amu_get_version(void);
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#if __aarch64__
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void amu_enable(bool el2_unused, cpu_context_t *ctx);
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#else
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void amu_enable(bool el2_unused);
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#endif
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/* Group 0 configuration helpers */
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uint64_t amu_group0_cnt_read(unsigned int idx);
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void amu_group0_cnt_write(unsigned int idx, uint64_t val);
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#if __aarch64__
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uint64_t amu_group0_voffset_read(unsigned int idx);
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void amu_group0_voffset_write(unsigned int idx, uint64_t val);
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#endif
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#if AMU_GROUP1_NR_COUNTERS
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bool amu_group1_supported(void);
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/* Group 1 configuration helpers */
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uint64_t amu_group1_cnt_read(unsigned int idx);
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void amu_group1_cnt_write(unsigned int idx, uint64_t val);
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void amu_group1_set_evtype(unsigned int idx, unsigned int val);
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#if __aarch64__
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uint64_t amu_group1_voffset_read(unsigned int idx);
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void amu_group1_voffset_write(unsigned int idx, uint64_t val);
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#endif
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#endif
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#endif /* AMU_H */
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@ -9,6 +9,72 @@
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#include <stdint.h>
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#include <lib/cassert.h>
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#include <lib/extensions/amu.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* All group 0 counters */
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#define AMU_GROUP0_COUNTERS_MASK U(0xf)
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#define AMU_GROUP0_NR_COUNTERS U(4)
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#define AMU_GROUP1_COUNTERS_MASK U(0)
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/* Calculate number of group 1 counters */
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#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15))
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#define AMU_GROUP1_NR_COUNTERS 16U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14))
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#define AMU_GROUP1_NR_COUNTERS 15U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13))
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#define AMU_GROUP1_NR_COUNTERS 14U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12))
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#define AMU_GROUP1_NR_COUNTERS 13U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11))
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#define AMU_GROUP1_NR_COUNTERS 12U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10))
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#define AMU_GROUP1_NR_COUNTERS 11U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9))
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#define AMU_GROUP1_NR_COUNTERS 10U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8))
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#define AMU_GROUP1_NR_COUNTERS 9U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7))
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#define AMU_GROUP1_NR_COUNTERS 8U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6))
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#define AMU_GROUP1_NR_COUNTERS 7U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5))
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#define AMU_GROUP1_NR_COUNTERS 6U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4))
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#define AMU_GROUP1_NR_COUNTERS 5U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3))
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#define AMU_GROUP1_NR_COUNTERS 4U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2))
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#define AMU_GROUP1_NR_COUNTERS 3U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1))
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#define AMU_GROUP1_NR_COUNTERS 2U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0))
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#define AMU_GROUP1_NR_COUNTERS 1U
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#else
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#define AMU_GROUP1_NR_COUNTERS 0U
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#endif
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CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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#if __aarch64__
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/* Architected event counter 1 does not have an offset register. */
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uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1];
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#endif
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#if AMU_GROUP1_NR_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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#if __aarch64__
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uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS];
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#endif
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#endif
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};
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uint64_t amu_group0_cnt_read_internal(unsigned int idx);
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void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
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@ -25,7 +25,7 @@ static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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* ID_PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6)
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* ID_PFR0_AMU_NOT_SUPPORTED: not supported
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*/
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unsigned int amu_get_version(void)
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static unsigned int amu_get_version(void)
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{
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return (unsigned int)(read_id_pfr0() >> ID_PFR0_AMU_SHIFT) &
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ID_PFR0_AMU_MASK;
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@ -33,7 +33,7 @@ unsigned int amu_get_version(void)
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#if AMU_GROUP1_NR_COUNTERS
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/* Check if group 1 counters is implemented */
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bool amu_group1_supported(void)
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static bool amu_group1_supported(void)
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{
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uint32_t features = read_amcfgr() >> AMCFGR_NCG_SHIFT;
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@ -113,7 +113,7 @@ void amu_enable(bool el2_unused)
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(unsigned int idx)
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static uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -122,7 +122,7 @@ uint64_t amu_group0_cnt_read(unsigned int idx)
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}
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/* Write the group 0 counter identified by the given `idx` with `val` */
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void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -133,7 +133,7 @@ void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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#if AMU_GROUP1_NR_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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uint64_t amu_group1_cnt_read(unsigned int idx)
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static uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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@ -143,7 +143,7 @@ uint64_t amu_group1_cnt_read(unsigned int idx)
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}
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/* Write the group 1 counter identified by the given `idx` with `val` */
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void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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@ -152,20 +152,6 @@ void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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/*
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* Program the event type register for the given `idx` with
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* the event number `val`
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*/
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void amu_group1_set_evtype(unsigned int idx, unsigned int val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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#endif /* AMU_GROUP1_NR_COUNTERS */
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static void *amu_context_save(const void *arg)
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@ -26,7 +26,7 @@ static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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* ID_AA64PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6)
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* ID_AA64PFR0_AMU_NOT_SUPPORTED: not supported
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*/
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unsigned int amu_get_version(void)
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static unsigned int amu_get_version(void)
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{
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return (unsigned int)(read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
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ID_AA64PFR0_AMU_MASK;
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@ -34,7 +34,7 @@ unsigned int amu_get_version(void)
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#if AMU_GROUP1_NR_COUNTERS
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/* Check if group 1 counters is implemented */
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bool amu_group1_supported(void)
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static bool amu_group1_supported(void)
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{
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uint64_t features = read_amcfgr_el0() >> AMCFGR_EL0_NCG_SHIFT;
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@ -130,7 +130,7 @@ void amu_enable(bool el2_unused, cpu_context_t *ctx)
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(unsigned int idx)
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static uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -139,7 +139,7 @@ uint64_t amu_group0_cnt_read(unsigned int idx)
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}
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/* Write the group 0 counter identified by the given `idx` with `val` */
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void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -154,7 +154,7 @@ void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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uint64_t amu_group0_voffset_read(unsigned int idx)
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static uint64_t amu_group0_voffset_read(unsigned int idx)
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{
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assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -169,7 +169,7 @@ uint64_t amu_group0_voffset_read(unsigned int idx)
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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void amu_group0_voffset_write(unsigned int idx, uint64_t val)
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static void amu_group0_voffset_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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@ -181,7 +181,7 @@ void amu_group0_voffset_write(unsigned int idx, uint64_t val)
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#if AMU_GROUP1_NR_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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uint64_t amu_group1_cnt_read(unsigned int idx)
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static uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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@ -191,7 +191,7 @@ uint64_t amu_group1_cnt_read(unsigned int idx)
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}
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/* Write the group 1 counter identified by the given `idx` with `val` */
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void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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@ -206,7 +206,7 @@ void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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uint64_t amu_group1_voffset_read(unsigned int idx)
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static uint64_t amu_group1_voffset_read(unsigned int idx)
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{
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assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
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assert(amu_group1_supported());
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@ -222,7 +222,7 @@ uint64_t amu_group1_voffset_read(unsigned int idx)
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*
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* Using this function requires FEAT_AMUv1p1 support.
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*/
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void amu_group1_voffset_write(unsigned int idx, uint64_t val)
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static void amu_group1_voffset_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
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assert(amu_group1_supported());
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amu_group1_voffset_write_internal(idx, val);
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isb();
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}
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/*
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* Program the event type register for the given `idx` with
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* the event number `val`
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*/
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void amu_group1_set_evtype(unsigned int idx, unsigned int val)
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{
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assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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#endif /* AMU_GROUP1_NR_COUNTERS */
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static void *amu_context_save(const void *arg)
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