plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to specify the TZC memory regions on sgi575, rdn1edge and rde1edge platforms. The default DMC-620 TZC memory regions are defined considering the support for secure paritition as well. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
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/*
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -7,7 +7,7 @@
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#include <platform_def.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <drivers/arm/tzc_dmc620.h>
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#include <sgi_dmc620_tzc_regions.h>
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uintptr_t rde1edge_dmc_base[] = {
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uintptr_t rde1edge_dmc_base[] = {
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RDE1EDGE_DMC620_BASE0,
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RDE1EDGE_DMC620_BASE0,
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@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
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};
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};
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static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
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static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
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{
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CSS_SGI_DMC620_TZC_REGIONS_DEF
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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};
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static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
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static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include <platform_def.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <drivers/arm/tzc_dmc620.h>
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#include <sgi_dmc620_tzc_regions.h>
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uintptr_t rdn1edge_dmc_base[] = {
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uintptr_t rdn1edge_dmc_base[] = {
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RDN1EDGE_DMC620_BASE0,
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RDN1EDGE_DMC620_BASE0,
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@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
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};
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};
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static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
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static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
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{
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CSS_SGI_DMC620_TZC_REGIONS_DEF
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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};
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static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
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static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
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/*
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include <platform_def.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <drivers/arm/tzc_dmc620.h>
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#include <sgi_dmc620_tzc_regions.h>
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#include <plat/arm/common/plat_arm.h>
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uintptr_t sgi575_dmc_base[] = {
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uintptr_t sgi575_dmc_base[] = {
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SGI575_DMC620_BASE0,
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SGI575_DMC620_BASE0,
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};
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};
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static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
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static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
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{
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CSS_SGI_DMC620_TZC_REGIONS_DEF
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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};
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static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
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static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SGI_DMC620_TZC_REGIONS_H
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#define SGI_DMC620_TZC_REGIONS_H
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#include <drivers/arm/tzc_dmc620.h>
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#if SPM_MM
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#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
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{ \
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.region_base = ARM_AP_TZC_DRAM1_BASE, \
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.region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
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.sec_attr = TZC_DMC620_REGION_S_RDWR \
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}, { \
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.region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \
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.region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \
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.sec_attr = TZC_DMC620_REGION_S_NS_RDWR \
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}, { \
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.region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \
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.region_top = ARM_AP_TZC_DRAM1_END, \
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.sec_attr = TZC_DMC620_REGION_S_RDWR \
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}
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#else
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#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
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{ \
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.region_base = ARM_AP_TZC_DRAM1_BASE, \
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.region_top = ARM_AP_TZC_DRAM1_END, \
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.sec_attr = TZC_DMC620_REGION_S_RDWR \
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}
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#endif /* SPM_MM */
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#endif /* SGI_DMC620_TZC_REGIONS_H */
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