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synquacer: Enable GICv3 support 

synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg 2018-06-15 14:58:25 +05:30
parent 0eb275c9a2
commit b529799ff1
4 changed files with 105 additions and 0 deletions
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3
plat/socionext/synquacer/include/platform_def.h
View File

@ -48,4 +48,7 @@
#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6
#define PLAT_SQ_GICD_BASE 0x30000000
#define PLAT_SQ_GICR_BASE 0x30400000
#endif /* __PLATFORM_DEF_H__ */

6
plat/socionext/synquacer/include/sq_common.h
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@ -15,4 +15,10 @@ void plat_sq_interconnect_exit_coherency(void);
unsigned int sq_calc_core_pos(u_register_t mpidr);
void sq_gic_driver_init(void);
void sq_gic_init(void);
void sq_gic_cpuif_enable(void);
void sq_gic_cpuif_disable(void);
void sq_gic_pcpu_init(void);
#endif /* __SQ_COMMON_H__ */

4
plat/socionext/synquacer/sq_bl31_setup.c
View File

@ -99,6 +99,10 @@ void bl31_platform_setup(void)
/* Initialize the CCN interconnect */
plat_sq_interconnect_init();
plat_sq_interconnect_enter_coherency();
/* Initialize the GIC driver, cpu and distributor interfaces */
sq_gic_driver_init();
sq_gic_init();
}
void bl31_plat_runtime_setup(void)

92
plat/socionext/synquacer/sq_gicv3.c Normal file
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@ -0,0 +1,92 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <gicv3.h>
#include <interrupt_props.h>
#include <platform.h>
#include <platform_def.h>
#include "sq_common.h"
static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT];
static const interrupt_prop_t sq_interrupt_props[] = {
/* G0 interrupts */
/* SGI0 */
INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
GIC_INTR_CFG_EDGE),
/* SGI6 */
INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
GIC_INTR_CFG_EDGE),
/* G1S interrupts */
/* Timer */
INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_LEVEL),
/* SGI1 */
INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE),
/* SGI2 */
INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE),
/* SGI3 */
INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE),
/* SGI4 */
INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE),
/* SGI5 */
INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE),
/* SGI7 */
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
GIC_INTR_CFG_EDGE)
};
static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
}
static const struct gicv3_driver_data sq_gic_driver_data = {
.gicd_base = PLAT_SQ_GICD_BASE,
.gicr_base = PLAT_SQ_GICR_BASE,
.interrupt_props = sq_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(sq_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = sq_rdistif_base_addrs,
.mpidr_to_core_pos = sq_mpidr_to_core_pos,
};
void sq_gic_driver_init(void)
{
gicv3_driver_init(&sq_gic_driver_data);
}
void sq_gic_init(void)
{
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
void sq_gic_cpuif_enable(void)
{
gicv3_cpuif_enable(plat_my_core_pos());
}
void sq_gic_cpuif_disable(void)
{
gicv3_cpuif_disable(plat_my_core_pos());
}
void sq_gic_pcpu_init(void)
{
gicv3_rdistif_init(plat_my_core_pos());
}