Tegra: introduce support for SMCCC_ARCH_SOC_ID

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC_ARCH_SOC_ID test.

<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
  TEST COMPLETE                                                 Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44
This commit is contained in:
Varun Wadekar 2020-05-12 14:04:10 -07:00 committed by varunw-nvidia
parent 4e2887f2da
commit b5b2923d9d
2 changed files with 34 additions and 0 deletions

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -259,3 +260,29 @@ bool tegra_platform_is_virt_dev_kit(void)
{
return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false);
}
/*
* This function returns soc version which mainly consist of below fields
*
* soc_version[30:24] = JEP-106 continuation code for the SiP
* soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
* soc_version[0:15] = chip identification
*/
int32_t plat_get_soc_version(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
return (int32_t)(manfid | (chip_id & 0xFFFF));
}
/*
* This function returns soc revision in below format
*
* soc_revision[8:15] = major version number
* soc_revision[0:7] = minor version number
*/
int32_t plat_get_soc_revision(void)
{
return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
}

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@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -30,6 +31,12 @@
#define TEGRA_CHIPID_TEGRA21 U(0x21)
#define TEGRA_CHIPID_TEGRA18 U(0x18)
/*******************************************************************************
* JEDEC Standard Manufacturer's Identification Code and Bank ID
******************************************************************************/
#define JEDEC_NVIDIA_MFID U(0x6B)
#define JEDEC_NVIDIA_BKID U(3)
#ifndef __ASSEMBLER__
/*