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Introduce arm_setup_page_tables() function 

This patch introduces the arm_setup_page_tables() function to
set up page tables on ARM platforms. It replaces the
arm_configure_mmu_elx() functions and does the same thing except
that it doesn't enable the MMU at the end. The idea is to reduce
the amount of per-EL code that is generated by the C preprocessor
by splitting the memory regions definitions and page tables creation
(which is generic) from the MMU enablement (which is the only per-EL
configuration).

As a consequence, the call to the enable_mmu_elx() function has been
moved up into the plat_arch_setup() hook. Any other ARM standard
platforms that use the functions `arm_configure_mmu_elx()` must be
updated.

Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
This commit is contained in:
Sandrine Bailleux 2016-05-18 16:11:47 +01:00
parent 6f511c4782
commit b5fa6563e6
11 changed files with 69 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
include/plat/arm/common/plat_arm.h
View File

@ -45,17 +45,7 @@
/*
* Utility functions common to ARM standard platforms
*/
void arm_configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit
#if USE_COHERENT_MEM
, unsigned long coh_start,
unsigned long coh_limit
#endif
);
void arm_configure_mmu_el3(unsigned long total_base,
void arm_setup_page_tables(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit

8
plat/arm/board/common/board_css_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,9 +31,9 @@
#include <plat_arm.h>
/*
* Table of regions for different BL stages to map using the MMU.
* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
* arm_configure_mmu_elx() will give the available subset of that,
* Table of memory regions for different BL stages to map using the MMU.
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
*/
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {

6
plat/arm/board/fvp/fvp_common.c
View File

@ -66,9 +66,9 @@ arm_config_t arm_config;
/*
* Table of regions for various BL stages to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* arm_configure_mmu_elx() will give the available subset of that,
* Table of memory regions for various BL stages to map using the MMU.
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
*/
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {

87
plat/arm/common/aarch64/arm_common.c
View File

@ -50,57 +50,48 @@ extern const mmap_region_t plat_arm_mmap[];
#pragma weak plat_get_syscnt_freq
#endif
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
/*
* Set up the page tables for the generic and platform-specific memory regions.
* The extents of the generic memory regions are specified by the function
* arguments and consist of:
* - Trusted SRAM seen by the BL image;
* - Read-only section (code and read-only data);
* - Coherent memory region, if applicable.
*/
void arm_setup_page_tables(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit
#if USE_COHERENT_MEM
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void arm_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add_region(coh_start, coh_start, \
coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(plat_arm_get_mmap()); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
#else
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void arm_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add(plat_arm_get_mmap()); \
init_xlat_tables(); \
\
enable_mmu_el##_el(0); \
}
,
unsigned long coh_start,
unsigned long coh_limit
#endif
)
{
/*
* Map the Trusted SRAM with appropriate memory attributes.
* Subsequent mappings will adjust the attributes for specific regions.
*/
mmap_add_region(total_base, total_base,
total_size,
MT_MEMORY | MT_RW | MT_SECURE);
/* Re-map the read-only section */
mmap_add_region(ro_start, ro_start,
ro_limit - ro_start,
MT_MEMORY | MT_RO | MT_SECURE);
#if USE_COHERENT_MEM
/* Re-map the coherent memory region */
mmap_add_region(coh_start, coh_start,
coh_limit - coh_start,
MT_DEVICE | MT_RW | MT_SECURE);
#endif
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_arm_get_mmap());
/* Define EL1 and EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
/* Create the page tables to reflect the above mappings */
init_xlat_tables();
}
uintptr_t plat_get_ns_image_entrypoint(void)
{

3
plat/arm/common/arm_bl1_setup.c
View File

@ -118,7 +118,7 @@ void bl1_early_platform_setup(void)
*****************************************************************************/
void arm_bl1_plat_arch_setup(void)
{
arm_configure_mmu_el3(bl1_tzram_layout.total_base,
arm_setup_page_tables(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT
@ -127,6 +127,7 @@ void arm_bl1_plat_arch_setup(void)
BL1_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el3(0);
}
void bl1_plat_arch_setup(void)

3
plat/arm/common/arm_bl2_setup.c
View File

@ -234,7 +234,7 @@ void bl2_platform_setup(void)
******************************************************************************/
void arm_bl2_plat_arch_setup(void)
{
arm_configure_mmu_el1(bl2_tzram_layout.total_base,
arm_setup_page_tables(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT
@ -243,6 +243,7 @@ void arm_bl2_plat_arch_setup(void)
BL2_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el1(0);
}
void bl2_plat_arch_setup(void)

5
plat/arm/common/arm_bl2u_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -102,7 +102,7 @@ void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info)
******************************************************************************/
void arm_bl2u_plat_arch_setup(void)
{
arm_configure_mmu_el1(BL2U_RO_LIMIT,
arm_setup_page_tables(BL2U_RO_LIMIT,
BL31_LIMIT,
BL2U_RO_BASE,
BL2U_RO_LIMIT
@ -112,6 +112,7 @@ void arm_bl2u_plat_arch_setup(void)
BL2U_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el1(0);
}
void bl2u_plat_arch_setup(void)

9
plat/arm/common/arm_bl31_setup.c
View File

@ -246,12 +246,14 @@ void bl31_plat_runtime_setup(void)
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
* Perform the very early platform specific architectural setup shared between
* ARM standard platforms. This only does basic initialization. Later
* architectural setup (bl31_arch_setup()) does not do anything platform
* specific.
******************************************************************************/
void arm_bl31_plat_arch_setup(void)
{
arm_configure_mmu_el3(BL31_RO_BASE,
arm_setup_page_tables(BL31_RO_BASE,
(BL31_END - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT
@ -260,6 +262,7 @@ void arm_bl31_plat_arch_setup(void)
BL31_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el3(0);
}
void bl31_plat_arch_setup(void)

5
plat/arm/common/tsp/arm_tsp_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -98,7 +98,7 @@ void tsp_platform_setup(void)
******************************************************************************/
void tsp_plat_arch_setup(void)
{
arm_configure_mmu_el1(BL32_RO_BASE,
arm_setup_page_tables(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT
@ -107,4 +107,5 @@ void tsp_plat_arch_setup(void)
BL32_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el1(0);
}

6
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View File

@ -147,18 +147,18 @@ void bl31_plat_runtime_setup(void)
}
/*
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU in a quick and dirty way.
* Perform the very early platform specific architectural setup here.
*/
void bl31_plat_arch_setup(void)
{
plat_arm_interconnect_init();
plat_arm_interconnect_enter_coherency();
arm_configure_mmu_el3(BL31_RO_BASE,
arm_setup_page_tables(BL31_RO_BASE,
BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
enable_mmu_el3(0);
}

5
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -90,7 +90,7 @@ void tsp_platform_setup(void)
******************************************************************************/
void tsp_plat_arch_setup(void)
{
arm_configure_mmu_el1(BL32_RO_BASE,
arm_setup_page_tables(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT
@ -99,4 +99,5 @@ void tsp_plat_arch_setup(void)
BL32_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el1(0);
}