Introduce arm_setup_page_tables() function
This patch introduces the arm_setup_page_tables() function to set up page tables on ARM platforms. It replaces the arm_configure_mmu_elx() functions and does the same thing except that it doesn't enable the MMU at the end. The idea is to reduce the amount of per-EL code that is generated by the C preprocessor by splitting the memory regions definitions and page tables creation (which is generic) from the MMU enablement (which is the only per-EL configuration). As a consequence, the call to the enable_mmu_elx() function has been moved up into the plat_arch_setup() hook. Any other ARM standard platforms that use the functions `arm_configure_mmu_elx()` must be updated. Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
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@ -45,17 +45,7 @@
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/*
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* Utility functions common to ARM standard platforms
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*/
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void arm_configure_mmu_el1(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit
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#if USE_COHERENT_MEM
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, unsigned long coh_start,
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unsigned long coh_limit
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#endif
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);
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void arm_configure_mmu_el3(unsigned long total_base,
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void arm_setup_page_tables(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -31,9 +31,9 @@
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#include <plat_arm.h>
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/*
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* Table of regions for different BL stages to map using the MMU.
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* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
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* arm_configure_mmu_elx() will give the available subset of that,
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* Table of memory regions for different BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as arm_setup_page_tables() already
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* takes care of mapping it.
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*/
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#if IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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@ -66,9 +66,9 @@ arm_config_t arm_config;
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/*
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* Table of regions for various BL stages to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* arm_configure_mmu_elx() will give the available subset of that,
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* Table of memory regions for various BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as arm_setup_page_tables() already
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* takes care of mapping it.
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*/
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#if IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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@ -50,57 +50,48 @@ extern const mmap_region_t plat_arm_mmap[];
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#pragma weak plat_get_syscnt_freq
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#endif
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/*******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Read-only section (code and read-only data);
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* - Coherent memory region, if applicable.
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*/
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void arm_setup_page_tables(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit
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#if USE_COHERENT_MEM
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void arm_configure_mmu_el##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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unsigned long coh_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add_region(coh_start, coh_start, \
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coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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mmap_add(plat_arm_get_mmap()); \
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init_xlat_tables(); \
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\
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enable_mmu_el##_el(0); \
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}
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#else
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void arm_configure_mmu_el##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add(plat_arm_get_mmap()); \
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init_xlat_tables(); \
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\
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enable_mmu_el##_el(0); \
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}
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,
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unsigned long coh_start,
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unsigned long coh_limit
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#endif
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)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the read-only section */
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mmap_add_region(ro_start, ro_start,
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ro_limit - ro_start,
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MT_MEMORY | MT_RO | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Re-map the coherent memory region */
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_arm_get_mmap());
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/* Define EL1 and EL3 variants of the function initialising the MMU */
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DEFINE_CONFIGURE_MMU_EL(1)
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DEFINE_CONFIGURE_MMU_EL(3)
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/* Create the page tables to reflect the above mappings */
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init_xlat_tables();
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}
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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@ -118,7 +118,7 @@ void bl1_early_platform_setup(void)
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*****************************************************************************/
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void arm_bl1_plat_arch_setup(void)
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{
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arm_configure_mmu_el3(bl1_tzram_layout.total_base,
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arm_setup_page_tables(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE,
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BL1_RO_LIMIT
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@ -127,6 +127,7 @@ void arm_bl1_plat_arch_setup(void)
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BL1_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl1_plat_arch_setup(void)
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@ -234,7 +234,7 @@ void bl2_platform_setup(void)
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******************************************************************************/
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void arm_bl2_plat_arch_setup(void)
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{
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arm_configure_mmu_el1(bl2_tzram_layout.total_base,
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arm_setup_page_tables(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE,
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BL2_RO_LIMIT
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@ -243,6 +243,7 @@ void arm_bl2_plat_arch_setup(void)
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BL2_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el1(0);
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}
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void bl2_plat_arch_setup(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -102,7 +102,7 @@ void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info)
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******************************************************************************/
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void arm_bl2u_plat_arch_setup(void)
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{
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arm_configure_mmu_el1(BL2U_RO_LIMIT,
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arm_setup_page_tables(BL2U_RO_LIMIT,
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BL31_LIMIT,
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BL2U_RO_BASE,
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BL2U_RO_LIMIT
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@ -112,6 +112,7 @@ void arm_bl2u_plat_arch_setup(void)
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BL2U_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el1(0);
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}
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void bl2u_plat_arch_setup(void)
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@ -246,12 +246,14 @@ void bl31_plat_runtime_setup(void)
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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* Perform the very early platform specific architectural setup shared between
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* ARM standard platforms. This only does basic initialization. Later
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* architectural setup (bl31_arch_setup()) does not do anything platform
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* specific.
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******************************************************************************/
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void arm_bl31_plat_arch_setup(void)
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{
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arm_configure_mmu_el3(BL31_RO_BASE,
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arm_setup_page_tables(BL31_RO_BASE,
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(BL31_END - BL31_RO_BASE),
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BL31_RO_BASE,
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BL31_RO_LIMIT
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@ -260,6 +262,7 @@ void arm_bl31_plat_arch_setup(void)
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BL31_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl31_plat_arch_setup(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -98,7 +98,7 @@ void tsp_platform_setup(void)
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******************************************************************************/
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void tsp_plat_arch_setup(void)
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{
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arm_configure_mmu_el1(BL32_RO_BASE,
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arm_setup_page_tables(BL32_RO_BASE,
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(BL32_END - BL32_RO_BASE),
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BL32_RO_BASE,
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BL32_RO_LIMIT
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BL32_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el1(0);
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}
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@ -147,18 +147,18 @@ void bl31_plat_runtime_setup(void)
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}
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/*
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the MMU in a quick and dirty way.
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* Perform the very early platform specific architectural setup here.
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*/
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void bl31_plat_arch_setup(void)
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{
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plat_arm_interconnect_init();
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plat_arm_interconnect_enter_coherency();
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arm_configure_mmu_el3(BL31_RO_BASE,
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arm_setup_page_tables(BL31_RO_BASE,
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BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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enable_mmu_el3(0);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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******************************************************************************/
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void tsp_plat_arch_setup(void)
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{
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arm_configure_mmu_el1(BL32_RO_BASE,
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arm_setup_page_tables(BL32_RO_BASE,
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(BL32_END - BL32_RO_BASE),
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BL32_RO_BASE,
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BL32_RO_LIMIT
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BL32_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_el1(0);
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}
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