rcar_gen3: drivers: ddr_a: Add D3 DDR init
Add R-Car D3 DDR initialization code. The code is in staging and needs cleanup, and possibly can even be merged with the E3 init code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut
parent
cdea546d70
commit
b60b9b5a66
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@ -6,8 +6,10 @@
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ifeq (${RCAR_LSI},${RCAR_E3})
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include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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else ifeq (${RCAR_LSI},${RCAR_D3})
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include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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else
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include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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endif
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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@ -0,0 +1,208 @@
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Revision history
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*
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* rev.0.01 2017/05/22 New
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*/
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#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_
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#define BOOT_INIT_DRAM_REGDEF_D3_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define BIT0 0x00000001U
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#define BIT30 0x40000000U
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/* DBSC registers */
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#define DBSC_D3_DBSYSCONF1 0xE6790004U
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#define DBSC_D3_DBPHYCONF0 0xE6790010U
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#define DBSC_D3_DBKIND 0xE6790020U
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#define DBSC_D3_DBMEMCONF00 0xE6790030U
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#define DBSC_D3_DBMEMCONF01 0xE6790034U
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#define DBSC_D3_DBMEMCONF02 0xE6790038U
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#define DBSC_D3_DBMEMCONF03 0xE679003CU
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#define DBSC_D3_DBMEMCONF10 0xE6790040U
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#define DBSC_D3_DBMEMCONF11 0xE6790044U
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#define DBSC_D3_DBMEMCONF12 0xE6790048U
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#define DBSC_D3_DBMEMCONF13 0xE679004CU
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#define DBSC_D3_DBMEMCONF20 0xE6790050U
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#define DBSC_D3_DBMEMCONF21 0xE6790054U
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#define DBSC_D3_DBMEMCONF22 0xE6790058U
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#define DBSC_D3_DBMEMCONF23 0xE679005CU
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#define DBSC_D3_DBMEMCONF30 0xE6790060U
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#define DBSC_D3_DBMEMCONF31 0xE6790064U
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#define DBSC_D3_DBMEMCONF32 0xE6790068U
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#define DBSC_D3_DBMEMCONF33 0xE679006CU
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#define DBSC_D3_DBSYSCNT0 0xE6790100U
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#define DBSC_D3_DBSVCR1 0xE6790104U
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#define DBSC_D3_DBSTATE0 0xE6790108U
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#define DBSC_D3_DBSTATE1 0xE679010CU
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#define DBSC_D3_DBINTEN 0xE6790180U
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#define DBSC_D3_DBINTSTAT0 0xE6790184U
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#define DBSC_D3_DBACEN 0xE6790200U
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#define DBSC_D3_DBRFEN 0xE6790204U
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#define DBSC_D3_DBCMD 0xE6790208U
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#define DBSC_D3_DBWAIT 0xE6790210U
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#define DBSC_D3_DBSYSCTRL0 0xE6790280U
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#define DBSC_D3_DBTR0 0xE6790300U
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#define DBSC_D3_DBTR1 0xE6790304U
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#define DBSC_D3_DBTR2 0xE6790308U
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#define DBSC_D3_DBTR3 0xE679030CU
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#define DBSC_D3_DBTR4 0xE6790310U
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#define DBSC_D3_DBTR5 0xE6790314U
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#define DBSC_D3_DBTR6 0xE6790318U
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#define DBSC_D3_DBTR7 0xE679031CU
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#define DBSC_D3_DBTR8 0xE6790320U
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#define DBSC_D3_DBTR9 0xE6790324U
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#define DBSC_D3_DBTR10 0xE6790328U
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#define DBSC_D3_DBTR11 0xE679032CU
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#define DBSC_D3_DBTR12 0xE6790330U
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#define DBSC_D3_DBTR13 0xE6790334U
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#define DBSC_D3_DBTR14 0xE6790338U
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#define DBSC_D3_DBTR15 0xE679033CU
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#define DBSC_D3_DBTR16 0xE6790340U
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#define DBSC_D3_DBTR17 0xE6790344U
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#define DBSC_D3_DBTR18 0xE6790348U
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#define DBSC_D3_DBTR19 0xE679034CU
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#define DBSC_D3_DBTR20 0xE6790350U
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#define DBSC_D3_DBTR21 0xE6790354U
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#define DBSC_D3_DBTR22 0xE6790358U
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#define DBSC_D3_DBTR24 0xE6790360U
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#define DBSC_D3_DBTR25 0xE6790364U
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#define DBSC_D3_DBBL 0xE6790400U
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#define DBSC_D3_DBRFCNF1 0xE6790414U
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#define DBSC_D3_DBRFCNF2 0xE6790418U
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#define DBSC_D3_DBCALCNF 0xE6790424U
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#define DBSC_D3_DBRNK2 0xE6790438U
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#define DBSC_D3_DBRNK3 0xE679043CU
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#define DBSC_D3_DBRNK4 0xE6790440U
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#define DBSC_D3_DBRNK5 0xE6790444U
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#define DBSC_D3_DBPDNCNF 0xE6790450U
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#define DBSC_D3_DBODT0 0xE6790460U
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#define DBSC_D3_DBODT1 0xE6790464U
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#define DBSC_D3_DBODT2 0xE6790468U
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#define DBSC_D3_DBODT3 0xE679046CU
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#define DBSC_D3_DBADJ0 0xE6790500U
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#define DBSC_D3_DBDBICNT 0xE6790518U
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#define DBSC_D3_DBDFICUPDCNF 0xE679052CU
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#define DBSC_D3_DBDFICNT0 0xE6790604U
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#define DBSC_D3_DBPDLK0 0xE6790620U
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#define DBSC_D3_DBPDRGA0 0xE6790624U
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#define DBSC_D3_DBPDRGD0 0xE6790628U
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#define DBSC_D3_DBPDSTAT00 0xE6790630U
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#define DBSC_D3_DBDFISTAT1 0xE6790640U
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#define DBSC_D3_DBDFICNT1 0xE6790644U
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#define DBSC_D3_DBPDLK1 0xE6790660U
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#define DBSC_D3_DBPDRGA1 0xE6790664U
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#define DBSC_D3_DBPDRGD1 0xE6790668U
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#define DBSC_D3_DBDFICNT2 0xE6790684U
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#define DBSC_D3_DBPDLK2 0xE67906A0U
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#define DBSC_D3_DBPDRGA2 0xE67906A4U
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#define DBSC_D3_DBPDRGD2 0xE67906A8U
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#define DBSC_D3_DBPDSTAT20 0xE67906B0U
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#define DBSC_D3_DBDFISTAT3 0xE67906C0U
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#define DBSC_D3_DBDFICNT3 0xE67906C4U
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#define DBSC_D3_DBPDLK3 0xE67906E0U
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#define DBSC_D3_DBPDRGA3 0xE67906E4U
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#define DBSC_D3_DBPDRGD3 0xE67906E8U
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#define DBSC_D3_DBBUS0CNF1 0xE6790804U
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#define DBSC_D3_DBCAM0CNF1 0xE6790904U
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#define DBSC_D3_DBCAM0CNF2 0xE6790908U
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#define DBSC_D3_DBCAM0STAT0 0xE6790980U
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#define DBSC_D3_DBCAM1STAT0 0xE6790990U
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#define DBSC_D3_DBBCAMDIS 0xE67909FCU
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#define DBSC_D3_DBSCHCNT0 0xE6791000U
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#define DBSC_D3_DBSCHSZ0 0xE6791010U
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#define DBSC_D3_DBSCHRW0 0xE6791020U
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#define DBSC_D3_DBSCHRW1 0xE6791024U
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#define DBSC_D3_DBSCHQOS00 0xE6791030U
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#define DBSC_D3_DBSCHQOS01 0xE6791034U
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#define DBSC_D3_DBSCHQOS02 0xE6791038U
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#define DBSC_D3_DBSCHQOS03 0xE679103CU
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#define DBSC_D3_DBSCHQOS10 0xE6791040U
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#define DBSC_D3_DBSCHQOS11 0xE6791044U
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#define DBSC_D3_DBSCHQOS12 0xE6791048U
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#define DBSC_D3_DBSCHQOS13 0xE679104CU
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#define DBSC_D3_DBSCHQOS20 0xE6791050U
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#define DBSC_D3_DBSCHQOS21 0xE6791054U
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#define DBSC_D3_DBSCHQOS22 0xE6791058U
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#define DBSC_D3_DBSCHQOS23 0xE679105CU
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#define DBSC_D3_DBSCHQOS30 0xE6791060U
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#define DBSC_D3_DBSCHQOS31 0xE6791064U
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#define DBSC_D3_DBSCHQOS32 0xE6791068U
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#define DBSC_D3_DBSCHQOS33 0xE679106CU
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#define DBSC_D3_DBSCHQOS40 0xE6791070U
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#define DBSC_D3_DBSCHQOS41 0xE6791074U
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#define DBSC_D3_DBSCHQOS42 0xE6791078U
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#define DBSC_D3_DBSCHQOS43 0xE679107CU
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#define DBSC_D3_DBSCHQOS50 0xE6791080U
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#define DBSC_D3_DBSCHQOS51 0xE6791084U
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#define DBSC_D3_DBSCHQOS52 0xE6791088U
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#define DBSC_D3_DBSCHQOS53 0xE679108CU
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#define DBSC_D3_DBSCHQOS60 0xE6791090U
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#define DBSC_D3_DBSCHQOS61 0xE6791094U
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#define DBSC_D3_DBSCHQOS62 0xE6791098U
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#define DBSC_D3_DBSCHQOS63 0xE679109CU
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#define DBSC_D3_DBSCHQOS70 0xE67910A0U
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#define DBSC_D3_DBSCHQOS71 0xE67910A4U
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#define DBSC_D3_DBSCHQOS72 0xE67910A8U
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#define DBSC_D3_DBSCHQOS73 0xE67910ACU
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#define DBSC_D3_DBSCHQOS80 0xE67910B0U
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#define DBSC_D3_DBSCHQOS81 0xE67910B4U
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#define DBSC_D3_DBSCHQOS82 0xE67910B8U
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#define DBSC_D3_DBSCHQOS83 0xE67910BCU
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#define DBSC_D3_DBSCHQOS90 0xE67910C0U
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#define DBSC_D3_DBSCHQOS91 0xE67910C4U
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#define DBSC_D3_DBSCHQOS92 0xE67910C8U
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#define DBSC_D3_DBSCHQOS93 0xE67910CCU
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#define DBSC_D3_DBSCHQOS100 0xE67910D0U
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#define DBSC_D3_DBSCHQOS101 0xE67910D4U
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#define DBSC_D3_DBSCHQOS102 0xE67910D8U
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#define DBSC_D3_DBSCHQOS103 0xE67910DCU
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#define DBSC_D3_DBSCHQOS110 0xE67910E0U
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#define DBSC_D3_DBSCHQOS111 0xE67910E4U
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#define DBSC_D3_DBSCHQOS112 0xE67910E8U
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#define DBSC_D3_DBSCHQOS113 0xE67910ECU
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#define DBSC_D3_DBSCHQOS120 0xE67910F0U
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#define DBSC_D3_DBSCHQOS121 0xE67910F4U
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#define DBSC_D3_DBSCHQOS122 0xE67910F8U
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#define DBSC_D3_DBSCHQOS123 0xE67910FCU
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#define DBSC_D3_DBSCHQOS130 0xE6791100U
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#define DBSC_D3_DBSCHQOS131 0xE6791104U
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#define DBSC_D3_DBSCHQOS132 0xE6791108U
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#define DBSC_D3_DBSCHQOS133 0xE679110CU
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#define DBSC_D3_DBSCHQOS140 0xE6791110U
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#define DBSC_D3_DBSCHQOS141 0xE6791114U
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#define DBSC_D3_DBSCHQOS142 0xE6791118U
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#define DBSC_D3_DBSCHQOS143 0xE679111CU
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#define DBSC_D3_DBSCHQOS150 0xE6791120U
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#define DBSC_D3_DBSCHQOS151 0xE6791124U
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#define DBSC_D3_DBSCHQOS152 0xE6791128U
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#define DBSC_D3_DBSCHQOS153 0xE679112CU
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#define DBSC_D3_SCFCTST0 0xE6791700U
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#define DBSC_D3_SCFCTST1 0xE6791708U
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#define DBSC_D3_SCFCTST2 0xE679170CU
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#define DBSC_D3_DBMRRDR0 0xE6791800U
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#define DBSC_D3_DBMRRDR1 0xE6791804U
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#define DBSC_D3_DBMRRDR2 0xE6791808U
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#define DBSC_D3_DBMRRDR3 0xE679180CU
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#define DBSC_D3_DBMRRDR4 0xE6791810U
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#define DBSC_D3_DBMRRDR5 0xE6791814U
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#define DBSC_D3_DBMRRDR6 0xE6791818U
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#define DBSC_D3_DBMRRDR7 0xE679181CU
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/
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@ -4,4 +4,8 @@
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${RCAR_LSI},${RCAR_E3})
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
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else
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
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endif
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@ -0,0 +1,691 @@
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <mmio.h>
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#include <common/debug.h>
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#include "boot_init_dram_regdef_d3.h"
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#define RCAR_DDR_VERSION "rev.0.01"
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#if RCAR_LSI != RCAR_D3
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#error "Don't have DDR initialize routine."
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#endif
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static void WriteReg_32(uint32_t a, uint32_t v)
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{
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(*(volatile uint32_t*)(uintptr_t)a) = v;
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}
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static uint32_t ReadReg_32(uint32_t a)
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{
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uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
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return w;
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}
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static void init_ddr_d3_1866(void)
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{
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uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
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WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
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WriteReg_32(DBSC_D3_DBKIND,0x00000007);
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WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
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WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
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WriteReg_32(DBSC_D3_DBTR0,0x0000000D);
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WriteReg_32(DBSC_D3_DBTR1,0x00000009);
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WriteReg_32(DBSC_D3_DBTR2,0x00000000);
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WriteReg_32(DBSC_D3_DBTR3,0x0000000D);
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WriteReg_32(DBSC_D3_DBTR4,0x000D000D);
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WriteReg_32(DBSC_D3_DBTR5,0x0000002D);
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WriteReg_32(DBSC_D3_DBTR6,0x00000020);
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WriteReg_32(DBSC_D3_DBTR7,0x00060006);
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WriteReg_32(DBSC_D3_DBTR8,0x00000021);
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WriteReg_32(DBSC_D3_DBTR9,0x00000007);
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WriteReg_32(DBSC_D3_DBTR10,0x0000000E);
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WriteReg_32(DBSC_D3_DBTR11,0x0000000C);
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WriteReg_32(DBSC_D3_DBTR12,0x00140014);
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WriteReg_32(DBSC_D3_DBTR13,0x000000F2);
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WriteReg_32(DBSC_D3_DBTR14,0x00170006);
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WriteReg_32(DBSC_D3_DBTR15,0x00060005);
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WriteReg_32(DBSC_D3_DBTR16,0x09210507);
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WriteReg_32(DBSC_D3_DBTR17,0x040E0000);
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WriteReg_32(DBSC_D3_DBTR18,0x00000200);
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WriteReg_32(DBSC_D3_DBTR19,0x012B004B);
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WriteReg_32(DBSC_D3_DBTR20,0x020000FB);
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WriteReg_32(DBSC_D3_DBTR21,0x00040004);
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WriteReg_32(DBSC_D3_DBBL,0x00000000);
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WriteReg_32(DBSC_D3_DBODT0,0x00000001);
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WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
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WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
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WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
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WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
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WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
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WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04);
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WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C);
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WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
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WriteReg_32(DBSC_D3_DBCMD,0x01000001);
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WriteReg_32(DBSC_D3_DBCMD,0x08000000);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
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while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
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WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
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WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
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WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
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WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
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WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
|
||||
while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
|
||||
RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
|
||||
RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
|
||||
RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
|
||||
WriteReg_32(DBSC_D3_DBCMD,0x08000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i<2; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
|
||||
RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
|
||||
if ( RegVal_R6 > 0 )
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
|
||||
} else
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
|
||||
}
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
|
||||
RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
|
||||
RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i < 2; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
|
||||
RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
|
||||
RegVal_R12 = (RegVal_R5 >> 0x2);
|
||||
if ( RegVal_R12 < RegVal_R6 )
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
|
||||
}
|
||||
else
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
|
||||
}
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
|
||||
while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
|
||||
WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
|
||||
WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23);
|
||||
WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
|
||||
WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
|
||||
WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBACEN,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
|
||||
WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
|
||||
WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
|
||||
WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
|
||||
WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
|
||||
WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
|
||||
WriteReg_32(0xE67F0018,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void init_ddr_d3_1600(void)
|
||||
{
|
||||
uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
|
||||
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
|
||||
WriteReg_32(DBSC_D3_DBKIND,0x00000007);
|
||||
WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
|
||||
WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBTR0,0x0000000B);
|
||||
WriteReg_32(DBSC_D3_DBTR1,0x00000008);
|
||||
WriteReg_32(DBSC_D3_DBTR2,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBTR3,0x0000000B);
|
||||
WriteReg_32(DBSC_D3_DBTR4,0x000B000B);
|
||||
WriteReg_32(DBSC_D3_DBTR5,0x00000027);
|
||||
WriteReg_32(DBSC_D3_DBTR6,0x0000001C);
|
||||
WriteReg_32(DBSC_D3_DBTR7,0x00060006);
|
||||
WriteReg_32(DBSC_D3_DBTR8,0x00000020);
|
||||
WriteReg_32(DBSC_D3_DBTR9,0x00000006);
|
||||
WriteReg_32(DBSC_D3_DBTR10,0x0000000C);
|
||||
WriteReg_32(DBSC_D3_DBTR11,0x0000000A);
|
||||
WriteReg_32(DBSC_D3_DBTR12,0x00120012);
|
||||
WriteReg_32(DBSC_D3_DBTR13,0x000000D0);
|
||||
WriteReg_32(DBSC_D3_DBTR14,0x00140005);
|
||||
WriteReg_32(DBSC_D3_DBTR15,0x00050004);
|
||||
WriteReg_32(DBSC_D3_DBTR16,0x071F0305);
|
||||
WriteReg_32(DBSC_D3_DBTR17,0x040C0000);
|
||||
WriteReg_32(DBSC_D3_DBTR18,0x00000200);
|
||||
WriteReg_32(DBSC_D3_DBTR19,0x01000040);
|
||||
WriteReg_32(DBSC_D3_DBTR20,0x020000D8);
|
||||
WriteReg_32(DBSC_D3_DBTR21,0x00040004);
|
||||
WriteReg_32(DBSC_D3_DBBL,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBODT0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
|
||||
WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
|
||||
WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
|
||||
WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04);
|
||||
WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
|
||||
WriteReg_32(DBSC_D3_DBCMD,0x01000001);
|
||||
WriteReg_32(DBSC_D3_DBCMD,0x08000000);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
|
||||
while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
|
||||
RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
|
||||
RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
|
||||
RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
|
||||
WriteReg_32(DBSC_D3_DBCMD,0x08000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i<2; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
|
||||
RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
|
||||
if ( RegVal_R6 > 0 )
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
|
||||
} else
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
|
||||
}
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
|
||||
RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
|
||||
RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i < 2; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
|
||||
RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
|
||||
RegVal_R12 = (RegVal_R5 >> 0x2);
|
||||
if ( RegVal_R12 < RegVal_R6 )
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
|
||||
}
|
||||
else
|
||||
{
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
|
||||
}
|
||||
}
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
|
||||
while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
|
||||
WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
|
||||
WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
|
||||
|
||||
WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
|
||||
WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
|
||||
WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30);
|
||||
WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
|
||||
WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
|
||||
WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBACEN,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
|
||||
WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
|
||||
WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
|
||||
WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
|
||||
WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
|
||||
WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
|
||||
WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
|
||||
WriteReg_32(0xE67F0018,0x00000001);
|
||||
WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_PRODUCT_D3 (0x00005800U)
|
||||
|
||||
#define RST_MODEMR (0xE6160060)
|
||||
#define MODEMR_MD19 (0x00080000U)
|
||||
|
||||
int32_t rcar_dram_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t ddr_mbps;
|
||||
|
||||
reg = mmio_read_32(PRR);
|
||||
|
||||
if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) {
|
||||
ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
|
||||
reg);
|
||||
panic();
|
||||
}
|
||||
|
||||
reg = mmio_read_32(RST_MODEMR);
|
||||
if (MODEMR_MD19 == (reg & MODEMR_MD19)) {
|
||||
init_ddr_d3_1866();
|
||||
ddr_mbps = 1866;
|
||||
} else {
|
||||
init_ddr_d3_1600();
|
||||
ddr_mbps = 1600;
|
||||
}
|
||||
|
||||
NOTICE("BL2: DDR%d\n", ddr_mbps);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue