mediatek: mt8192: add rtc power off sequence
add mt6359p rtc power off sequence and enable k_eosc mode Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com> Change-Id: I65450c63c44ccb5082541dbbe28b8aa0a95ecc56
This commit is contained in:
Yuchen Huang
Yidi Lin
parent
44ad5d67cf
commit
b686d33095
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@ -0,0 +1,148 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <rtc.h>
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static void RTC_Config_Interface(uint32_t addr, uint16_t data,
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uint16_t mask, uint16_t shift)
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{
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uint16_t pmic_reg;
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pmic_reg = RTC_Read(addr);
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pmic_reg &= ~(mask << shift);
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pmic_reg |= (data << shift);
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RTC_Write(addr, pmic_reg);
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}
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static int32_t rtc_disable_2sec_reboot(void)
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{
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uint16_t reboot;
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reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
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~RTC_BBPU_AUTO_PDN_SEL;
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RTC_Write(RTC_AL_SEC, reboot);
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return RTC_Write_Trigger();
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}
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static int32_t rtc_enable_k_eosc(void)
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{
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uint16_t alm_dow, alm_sec;
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int16_t ret;
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/* Turning on eosc cali mode clock */
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RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0_CLR, 1,
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PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
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PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
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alm_sec = RTC_Read(RTC_AL_SEC) & (~RTC_LPD_OPT_MASK);
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RTC_Write(RTC_AL_SEC, alm_sec);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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RTC_Write(RTC_CON, RTC_LPD_EN);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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RTC_Write(RTC_CON, RTC_LPD_RST);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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RTC_Write(RTC_CON, RTC_LPD_EN);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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RTC_Write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
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RTC_Write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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/* set RTC EOSC calibration period = 8sec */
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alm_dow = (RTC_Read(RTC_AL_DOW) & (~RTC_RG_EOSC_CALI_TD_MASK)) |
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RTC_RG_EOSC_CALI_TD_8SEC;
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RTC_Write(RTC_AL_DOW, alm_dow);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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RTC_Write(RTC_BBPU,
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RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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/* Enable K EOSC mode :use solution1 of eosc cali to fix mt6359p 32K*/
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RTC_Write(RTC_AL_YEA, (((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
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& (~RTC_K_EOSC_RSV_1)) | (RTC_K_EOSC_RSV_2)));
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return 0;
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}
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INFO("[RTC] RTC_enable_k_eosc\n");
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return 1;
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}
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void rtc_power_off_sequence(void)
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{
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uint16_t bbpu;
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int16_t ret;
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ret = rtc_disable_2sec_reboot();
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if (ret == 0) {
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return;
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}
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ret = rtc_enable_k_eosc();
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if (ret == 0) {
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return;
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}
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bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN;
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if (Writeif_unlock() != 0) {
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RTC_Write(RTC_BBPU,
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bbpu | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR);
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RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return;
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}
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mdelay(1);
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bbpu = RTC_Read(RTC_BBPU);
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if (((bbpu & RTC_BBPU_RESET_ALARM) > 0) ||
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((bbpu & RTC_BBPU_RESET_SPAR) > 0)) {
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INFO("[RTC] timeout\n");
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}
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bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
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RTC_Write(RTC_BBPU, bbpu);
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ret = RTC_Write_Trigger();
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if (ret == 0) {
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return;
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}
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}
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}
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@ -0,0 +1,197 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RTC_H
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#define RTC_H
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/* RTC registers */
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enum {
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RTC_BBPU = 0x0588,
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RTC_IRQ_STA = 0x058A,
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RTC_IRQ_EN = 0x058C,
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RTC_CII_EN = 0x058E
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};
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enum {
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RTC_AL_SEC = 0x05A0,
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RTC_AL_MIN = 0x05A2,
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RTC_AL_HOU = 0x05A4,
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RTC_AL_DOM = 0x05A6,
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RTC_AL_DOW = 0x05A8,
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RTC_AL_MTH = 0x05AA,
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RTC_AL_YEA = 0x05AC,
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RTC_AL_MASK = 0x0590
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};
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enum {
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RTC_OSC32CON = 0x05AE,
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RTC_CON = 0x05C4,
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RTC_WRTGR = 0x05C2
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};
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enum {
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RTC_POWERKEY1 = 0x05B0,
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RTC_POWERKEY2 = 0x05B2
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};
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enum {
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RTC_POWERKEY1_KEY = 0xA357,
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RTC_POWERKEY2_KEY = 0x67D2
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};
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enum {
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RTC_PDN1 = 0x05B4,
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RTC_PDN2 = 0x05B6,
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RTC_SPAR0 = 0x05B8,
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RTC_SPAR1 = 0x05BA,
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RTC_PROT = 0x05BC,
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RTC_DIFF = 0x05BE,
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RTC_CALI = 0x05C0
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};
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enum {
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RTC_OSC32CON_UNLOCK1 = 0x1A57,
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RTC_OSC32CON_UNLOCK2 = 0x2B68
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};
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enum {
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RTC_LPD_EN = 0x0406,
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RTC_LPD_RST = 0x040E
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};
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enum {
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RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
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RTC_LPD_OPT_EOSC_LPD = 1U << 13,
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RTC_LPD_OPT_XOSC_LPD = 2U << 13,
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RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
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};
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#define RTC_LPD_OPT_MASK (3U << 13)
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enum {
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RTC_PROT_UNLOCK1 = 0x586A,
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RTC_PROT_UNLOCK2 = 0x9136
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};
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enum {
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RTC_BBPU_PWREN = 1U << 0,
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RTC_BBPU_SPAR_SW = 1U << 1,
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RTC_BBPU_RESET_SPAR = 1U << 2,
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RTC_BBPU_RESET_ALARM = 1U << 3,
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RTC_BBPU_CLRPKY = 1U << 4,
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RTC_BBPU_RELOAD = 1U << 5,
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RTC_BBPU_CBUSY = 1U << 6
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};
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enum {
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RTC_AL_MASK_SEC = 1U << 0,
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RTC_AL_MASK_MIN = 1U << 1,
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RTC_AL_MASK_HOU = 1U << 2,
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RTC_AL_MASK_DOM = 1U << 3,
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RTC_AL_MASK_DOW = 1U << 4,
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RTC_AL_MASK_MTH = 1U << 5,
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RTC_AL_MASK_YEA = 1U << 6
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};
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enum {
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RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
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RTC_BBPU_2SEC_CK_SEL = 1U << 7,
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RTC_BBPU_2SEC_EN = 1U << 8,
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RTC_BBPU_2SEC_MODE = 0x3 << 9,
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RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
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RTC_BBPU_2SEC_STAT_STA = 1U << 12
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};
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enum {
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RTC_BBPU_KEY = 0x43 << 8
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};
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enum {
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RTC_EMBCK_SRC_SEL = 1 << 8,
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RTC_EMBCK_SEL_MODE = 3 << 6,
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RTC_XOSC32_ENB = 1 << 5,
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RTC_REG_XOSC32_ENB = 1 << 15
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};
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enum {
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RTC_K_EOSC_RSV_0 = 1 << 8,
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RTC_K_EOSC_RSV_1 = 1 << 9,
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RTC_K_EOSC_RSV_2 = 1 << 10
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};
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enum {
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RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
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RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
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RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
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RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
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RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
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RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
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};
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/* PMIC TOP Register Definition */
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enum {
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PMIC_RG_TOP_CON = 0x0020,
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PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
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PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
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PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
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PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
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PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
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PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
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};
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/* PMIC SCK Register Definition */
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enum {
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PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
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PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
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PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
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PMIC_RG_EOSC_CALI_CON0 = 0x53A
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};
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enum {
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PMIC_EOSC_CALI_START_ADDR = 0x53A
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};
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enum {
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PMIC_EOSC_CALI_START_MASK = 0x1,
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PMIC_EOSC_CALI_START_SHIFT = 0
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};
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/* PMIC DCXO Register Definition */
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enum {
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PMIC_RG_DCXO_CW00 = 0x0788,
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PMIC_RG_DCXO_CW02 = 0x0790,
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PMIC_RG_DCXO_CW08 = 0x079C,
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PMIC_RG_DCXO_CW09 = 0x079E,
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PMIC_RG_DCXO_CW09_CLR = 0x07A2,
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PMIC_RG_DCXO_CW10 = 0x07A4,
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PMIC_RG_DCXO_CW12 = 0x07A8,
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PMIC_RG_DCXO_CW13 = 0x07AA,
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PMIC_RG_DCXO_CW15 = 0x07AE,
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PMIC_RG_DCXO_CW19 = 0x07B6,
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};
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enum {
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PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
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PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
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PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
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PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
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PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
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PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
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PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
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PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
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PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
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PMIC_RG_XO_EN32K_MAN_SHIFT = 0
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};
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/* external API */
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uint16_t RTC_Read(uint32_t addr);
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void RTC_Write(uint32_t addr, uint16_t data);
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int32_t rtc_busy_wait(void);
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int32_t RTC_Write_Trigger(void);
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int32_t Writeif_unlock(void);
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void rtc_power_off_sequence(void);
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#endif /* RTC_H */
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@ -21,6 +21,7 @@
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#include <plat_params.h>
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#include <plat_pm.h>
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#include <pmic.h>
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#include <rtc.h>
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/*
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* Cluster state request:
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@ -341,6 +342,7 @@ static void __dead2 plat_mtk_system_off(void)
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{
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INFO("MTK System Off\n");
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rtc_power_off_sequence();
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pmic_power_off();
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wfi();
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@ -16,6 +16,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT_SOC}/drivers/mcdi/ \
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-I${MTK_PLAT_SOC}/drivers/pmic/ \
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-I${MTK_PLAT_SOC}/drivers/ptp3/ \
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-I${MTK_PLAT_SOC}/drivers/rtc/ \
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-I${MTK_PLAT_SOC}/drivers/spmc/ \
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-I${MTK_PLAT_SOC}/drivers/timer/ \
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-I${MTK_PLAT_SOC}/drivers/uart/
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@ -39,6 +40,7 @@ BL31_SOURCES += common/desc_image_load.c \
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lib/cpus/aarch64/cortex_a76.S \
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plat/common/plat_gicv3.c \
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${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
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${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
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${MTK_PLAT}/common/drivers/uart/uart.c \
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${MTK_PLAT}/common/mtk_plat_common.c \
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${MTK_PLAT}/common/mtk_sip_svc.c \
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@ -47,6 +49,7 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
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${MTK_PLAT_SOC}/bl31_plat_setup.c \
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${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
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${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
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${MTK_PLAT_SOC}/plat_pm.c \
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${MTK_PLAT_SOC}/plat_topology.c \
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${MTK_PLAT_SOC}/plat_mt_gic.c \
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