rcar_gen3: plat: Add R-Car V3M support
Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
This commit is contained in:
Valentine Barshak
Marek Vasut
parent
0a4bf763f3
commit
b709fe9c43
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@ -18,6 +18,8 @@
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#define BOARD_DEFAULT (BOARD_DRAAK << BOARD_CODE_SHIFT)
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#elif (RCAR_LSI == RCAR_E3)
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#define BOARD_DEFAULT (BOARD_EBISU << BOARD_CODE_SHIFT)
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#elif (RCAR_LSI == RCAR_V3M)
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#define BOARD_DEFAULT (BOARD_EAGLE << BOARD_CODE_SHIFT)
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#else
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#define BOARD_DEFAULT (BOARD_SALVATOR_X << BOARD_CODE_SHIFT)
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#endif
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@ -35,6 +37,7 @@
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#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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#define DR_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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#define EA_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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#define KK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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const char *g_board_tbl[] = {
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@ -46,6 +49,7 @@ const char *g_board_tbl[] = {
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[BOARD_KRIEK] = "Kriek",
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[BOARD_EBISU] = "Ebisu",
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[BOARD_DRAAK] = "Draak",
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[BOARD_EAGLE] = "Eagle",
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[BOARD_UNKNOWN] = "unknown"
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};
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@ -60,6 +64,7 @@ int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev)
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[BOARD_EBISU_4D] = EB4_ID,
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[BOARD_EBISU] = EB_ID,
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[BOARD_DRAAK] = DR_ID,
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[BOARD_EAGLE] = EA_ID,
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[BOARD_KRIEK] = KK_ID,
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};
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static uint8_t board_id = BOARD_ID_UNKNOWN;
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@ -16,7 +16,8 @@
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#define BOARD_STARTER_KIT_PRE (0x0B)
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#define BOARD_EBISU_4D (0x0DU)
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#define BOARD_DRAAK (0x0EU)
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#define BOARD_UNKNOWN (BOARD_DRAAK + 1U)
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#define BOARD_EAGLE (0x0FU)
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#define BOARD_UNKNOWN (BOARD_EAGLE + 1U)
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#define BOARD_REV_UNKNOWN (0xFF)
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@ -16,7 +16,11 @@
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#include "rcar_private.h"
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/* DMA CHANNEL setting (0/16/32) */
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#if RCAR_LSI == RCAR_V3M
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#define DMA_CH 16
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#else
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#define DMA_CH 0
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#endif
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#if (DMA_CH == 0)
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#define SYS_DMAC_BIT ((uint32_t)1U << 19U)
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@ -19,8 +19,9 @@ typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs);
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#define OLD_API_TABLE1 (0U) /* H3 Ver.1.0/Ver.1.1 */
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#define OLD_API_TABLE2 (1U) /* H3 Ver.2.0 */
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#define OLD_API_TABLE3 (2U) /* M3 Ver.1.0 */
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#define NEW_API_TABLE (3U) /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
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#define API_TABLE_MAX (4U) /* table max */
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#define NEW_API_TABLE (3U) /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3, V3M WS2.0 */
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#define NEW_API_TABLE2 (4U) /* V3M WS1.0 */
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#define API_TABLE_MAX (5U) /* table max */
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/* Later than H3 Ver.2.0 */
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static uint32_t get_table_index(void)
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@ -51,6 +52,14 @@ static uint32_t get_table_index(void)
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/* M3 Ver.1.1 or later */
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index = NEW_API_TABLE;
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break;
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case RCAR_PRODUCT_V3M:
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if (cut_ver == RCAR_CUT_VER10)
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/* V3M WS1.0 */
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index = NEW_API_TABLE2;
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else
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/* V3M WS2.0 or later */
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index = NEW_API_TABLE;
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break;
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default:
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index = NEW_API_TABLE;
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break;
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@ -66,7 +75,8 @@ uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
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0xEB10DD64U, /* H3 Ver.1.0/Ver.1.1 */
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0xEB116ED4U, /* H3 Ver.2.0 */
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0xEB1102FCU, /* M3 Ver.1.0 */
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0xEB100180U /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
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0xEB100180U, /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3, V3M WS2.0 */
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0xEB110128U, /* V3M WS1.0 */
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};
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rom_secure_boot_api_f secure_boot;
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uint32_t index;
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@ -83,7 +93,8 @@ uint32_t rcar_rom_get_lcs(uint32_t *lcs)
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0xEB10DFE0U, /* H3 Ver.1.0/Ver.1.1 */
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0xEB117150U, /* H3 Ver.2.0 */
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0xEB110578U, /* M3 Ver.1.0 */
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0xEB10018CU /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
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0xEB10018CU, /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3, V3M WS2.0 */
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0xEB1103A4U, /* V3M WS1.0 */
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};
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rom_get_lcs_api_f get_lcs;
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uint32_t index;
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@ -21,12 +21,16 @@
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/* module stop */
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#define CPG_BASE (0xE6150000)
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#define CPG_SMSTPCR2 (0x0138)
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#define CPG_SMSTPCR3 (0x013C)
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#define CPG_MSTPSR2 (0x0040)
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#define CPG_MSTPSR3 (0x0048)
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#define MSTP207 (1 << 7)
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#define MSTP310 (1 << 10)
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#define CPG_CPGWPR (0x0900)
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/* scif */
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#define SCIF0_BASE (0xE6E60000)
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#define SCIF2_BASE (0xE6E88000)
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#define SCIF_SCSMR (0x00)
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#define SCIF_SCBRR (0x04)
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@ -41,6 +45,18 @@
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#define SCIF_DL (0x30)
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#define SCIF_CKS (0x34)
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#if RCAR_LSI == RCAR_V3M
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#define SCIF_BASE SCIF0_BASE
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#define CPG_SMSTPCR CPG_SMSTPCR2
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#define CPG_MSTPSR CPG_MSTPSR2
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#define MSTP MSTP207
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#else
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#define SCIF_BASE SCIF2_BASE
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#define CPG_SMSTPCR CPG_SMSTPCR3
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#define CPG_MSTPSR CPG_MSTPSR3
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#define MSTP MSTP310
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#endif
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/* mode pin */
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#define RST_MODEMR (0xE6160060)
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#define MODEMR_MD12 (0x00001000)
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@ -152,17 +168,17 @@ endfunc console_uninit
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*/
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func console_core_init
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ldr x0, =CPG_BASE
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ldr w1, [x0, #CPG_SMSTPCR3]
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and w1, w1, #~MSTP310 /* MSTP310=0 */
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ldr w1, [x0, #CPG_SMSTPCR]
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and w1, w1, #~MSTP
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mvn w2, w1
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str w2, [x0, #CPG_CPGWPR]
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str w1, [x0, #CPG_SMSTPCR3]
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str w1, [x0, #CPG_SMSTPCR]
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5:
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ldr w1, [x0, #CPG_MSTPSR3]
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and w1, w1, #MSTP310
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ldr w1, [x0, #CPG_MSTPSR]
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and w1, w1, #MSTP
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cbnz w1, 5b
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ldr x0, =SCIF2_BASE
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ldr x0, =SCIF_BASE
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/* Clear bits TE and RE in SCSCR to 0 */
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mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS)
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strh w1, [x0, #SCIF_SCSCR]
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@ -272,7 +288,7 @@ endfunc console_putc
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* --------------------------------------------------------
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*/
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func console_core_putc
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ldr x1, =SCIF2_BASE
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ldr x1, =SCIF_BASE
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cmp w0, #0xA
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/* Prepend '\r' to '\n' */
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bne 2f
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@ -323,7 +339,7 @@ endfunc console_getc
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* ---------------------------------------------
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*/
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func console_flush
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ldr x0, =SCIF2_BASE
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ldr x0, =SCIF_BASE
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1:
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/* Check TEND flag */
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ldrh w1, [x0, #SCIF_SCFSR]
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@ -331,7 +347,7 @@ func console_flush
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cmp w1, #SCFSR_TEND_TRANS_END
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bne 1b
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ldr x0, =SCIF2_BASE
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ldr x0, =SCIF_BASE
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ldrh w1, [x0, #SCIF_SCSCR]
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and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
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strh w1, [x0, #SCIF_SCSCR]
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@ -9,6 +9,8 @@ ifeq (${RCAR_LSI},${RCAR_E3})
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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else ifeq (${RCAR_LSI},${RCAR_D3})
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include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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else ifeq (${RCAR_LSI},${RCAR_V3M})
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include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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else
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include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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@ -0,0 +1,296 @@
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/*
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* Copyright (c) 2015-2016, Renesas Electronics Corporation
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_
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#define BOOT_INIT_DRAM_REGDEF_V3M_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define BIT0 0x00000001U
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#define BIT30 0x40000000U
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/* DBSC registers */
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// modified , last 2016.12.08
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#define DBSC_V3M_DBSYSCONF0 0xE6790000U
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#define DBSC_V3M_DBSYSCONF1 0xE6790004U
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#define DBSC_V3M_DBPHYCONF0 0xE6790010U
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#define DBSC_V3M_DBKIND 0xE6790020U
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#define DBSC_V3M_DBMEMCONF00 0xE6790030U
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#define DBSC_V3M_DBMEMCONF01 0xE6790034U
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#define DBSC_V3M_DBMEMCONF02 0xE6790038U
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#define DBSC_V3M_DBMEMCONF03 0xE679003CU
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#define DBSC_V3M_DBMEMCONF10 0xE6790040U
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#define DBSC_V3M_DBMEMCONF11 0xE6790044U
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#define DBSC_V3M_DBMEMCONF12 0xE6790048U
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#define DBSC_V3M_DBMEMCONF13 0xE679004CU
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#define DBSC_V3M_DBMEMCONF20 0xE6790050U
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#define DBSC_V3M_DBMEMCONF21 0xE6790054U
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#define DBSC_V3M_DBMEMCONF22 0xE6790058U
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#define DBSC_V3M_DBMEMCONF23 0xE679005CU
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#define DBSC_V3M_DBMEMCONF30 0xE6790060U
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#define DBSC_V3M_DBMEMCONF31 0xE6790064U
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#define DBSC_V3M_DBMEMCONF32 0xE6790068U
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#define DBSC_V3M_DBMEMCONF33 0xE679006CU
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#define DBSC_V3M_DBSYSCNT0 0xE6790100U
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#define DBSC_V3M_DBSVCR1 0xE6790104U
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#define DBSC_V3M_DBSTATE0 0xE6790108U
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#define DBSC_V3M_DBSTATE1 0xE679010CU
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#define DBSC_V3M_DBINTEN 0xE6790180U
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#define DBSC_V3M_DBINTSTAT0 0xE6790184U
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#define DBSC_V3M_DBACEN 0xE6790200U
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#define DBSC_V3M_DBRFEN 0xE6790204U
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#define DBSC_V3M_DBCMD 0xE6790208U
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#define DBSC_V3M_DBWAIT 0xE6790210U
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#define DBSC_V3M_DBSYSCTRL0 0xE6790280U
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#define DBSC_V3M_DBTR0 0xE6790300U
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#define DBSC_V3M_DBTR1 0xE6790304U
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#define DBSC_V3M_DBTR2 0xE6790308U
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#define DBSC_V3M_DBTR3 0xE679030CU
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#define DBSC_V3M_DBTR4 0xE6790310U
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#define DBSC_V3M_DBTR5 0xE6790314U
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#define DBSC_V3M_DBTR6 0xE6790318U
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#define DBSC_V3M_DBTR7 0xE679031CU
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#define DBSC_V3M_DBTR8 0xE6790320U
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#define DBSC_V3M_DBTR9 0xE6790324U
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#define DBSC_V3M_DBTR10 0xE6790328U
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#define DBSC_V3M_DBTR11 0xE679032CU
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#define DBSC_V3M_DBTR12 0xE6790330U
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#define DBSC_V3M_DBTR13 0xE6790334U
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#define DBSC_V3M_DBTR14 0xE6790338U
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#define DBSC_V3M_DBTR15 0xE679033CU
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#define DBSC_V3M_DBTR16 0xE6790340U
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#define DBSC_V3M_DBTR17 0xE6790344U
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#define DBSC_V3M_DBTR18 0xE6790348U
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#define DBSC_V3M_DBTR19 0xE679034CU
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#define DBSC_V3M_DBTR20 0xE6790350U
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#define DBSC_V3M_DBTR21 0xE6790354U
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#define DBSC_V3M_DBTR22 0xE6790358U
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#define DBSC_V3M_DBTR23 0xE679035CU
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#define DBSC_V3M_DBTR24 0xE6790360U
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#define DBSC_V3M_DBTR25 0xE6790364U
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#define DBSC_V3M_DBBL 0xE6790400U
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#define DBSC_V3M_DBRFCNF1 0xE6790414U
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#define DBSC_V3M_DBRFCNF2 0xE6790418U
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#define DBSC_V3M_DBTSPCNF 0xE6790420U
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#define DBSC_V3M_DBCALCNF 0xE6790424U
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#define DBSC_V3M_DBRNK2 0xE6790438U
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#define DBSC_V3M_DBRNK3 0xE679043CU
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#define DBSC_V3M_DBRNK4 0xE6790440U
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#define DBSC_V3M_DBRNK5 0xE6790444U
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#define DBSC_V3M_DBPDNCNF 0xE6790450U
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#define DBSC_V3M_DBODT0 0xE6790460U
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#define DBSC_V3M_DBODT1 0xE6790464U
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#define DBSC_V3M_DBODT2 0xE6790468U
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#define DBSC_V3M_DBODT3 0xE679046CU
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#define DBSC_V3M_DBODT4 0xE6790470U
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#define DBSC_V3M_DBODT5 0xE6790474U
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#define DBSC_V3M_DBODT6 0xE6790478U
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#define DBSC_V3M_DBODT7 0xE679047CU
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#define DBSC_V3M_DBADJ0 0xE6790500U
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#define DBSC_V3M_DBDBICNT 0xE6790518U
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#define DBSC_V3M_DBDFIPMSTRCNF 0xE6790520U
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#define DBSC_V3M_DBDFIPMSTRSTAT 0xE6790524U
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#define DBSC_V3M_DBDFILPCNF 0xE6790528U
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#define DBSC_V3M_DBDFICUPDCNF 0xE679052CU
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#define DBSC_V3M_DBDFISTAT0 0xE6790600U
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#define DBSC_V3M_DBDFICNT0 0xE6790604U
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#define DBSC_V3M_DBPDCNT00 0xE6790610U
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#define DBSC_V3M_DBPDCNT01 0xE6790614U
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#define DBSC_V3M_DBPDCNT02 0xE6790618U
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#define DBSC_V3M_DBPDCNT03 0xE679061CU
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#define DBSC_V3M_DBPDLK0 0xE6790620U
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#define DBSC_V3M_DBPDRGA0 0xE6790624U
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#define DBSC_V3M_DBPDRGD0 0xE6790628U
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#define DBSC_V3M_DBPDSTAT00 0xE6790630U
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#define DBSC_V3M_DBDFISTAT1 0xE6790640U
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#define DBSC_V3M_DBDFICNT1 0xE6790644U
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#define DBSC_V3M_DBPDCNT10 0xE6790650U
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#define DBSC_V3M_DBPDCNT11 0xE6790654U
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#define DBSC_V3M_DBPDCNT12 0xE6790658U
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#define DBSC_V3M_DBPDCNT13 0xE679065CU
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#define DBSC_V3M_DBPDLK1 0xE6790660U
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#define DBSC_V3M_DBPDRGA1 0xE6790664U
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#define DBSC_V3M_DBPDRGD1 0xE6790668U
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#define DBSC_V3M_DBPDSTAT10 0xE6790670U
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#define DBSC_V3M_DBDFISTAT2 0xE6790680U
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#define DBSC_V3M_DBDFICNT2 0xE6790684U
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#define DBSC_V3M_DBPDCNT20 0xE6790690U
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#define DBSC_V3M_DBPDCNT21 0xE6790694U
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#define DBSC_V3M_DBPDCNT22 0xE6790698U
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#define DBSC_V3M_DBPDCNT23 0xE679069CU
|
||||
#define DBSC_V3M_DBPDLK2 0xE67906A0U
|
||||
#define DBSC_V3M_DBPDRGA2 0xE67906A4U
|
||||
#define DBSC_V3M_DBPDRGD2 0xE67906A8U
|
||||
#define DBSC_V3M_DBPDSTAT20 0xE67906B0U
|
||||
#define DBSC_V3M_DBDFISTAT3 0xE67906C0U
|
||||
#define DBSC_V3M_DBDFICNT3 0xE67906C4U
|
||||
#define DBSC_V3M_DBPDCNT30 0xE67906D0U
|
||||
#define DBSC_V3M_DBPDCNT31 0xE67906D4U
|
||||
#define DBSC_V3M_DBPDCNT32 0xE67906D8U
|
||||
#define DBSC_V3M_DBPDCNT33 0xE67906DCU
|
||||
#define DBSC_V3M_DBPDLK3 0xE67906E0U
|
||||
#define DBSC_V3M_DBPDRGA3 0xE67906E4U
|
||||
#define DBSC_V3M_DBPDRGD3 0xE67906E8U
|
||||
#define DBSC_V3M_DBPDSTAT30 0xE67906F0U
|
||||
#define DBSC_V3M_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_V3M_DBBUS0CNF1 0xE6790804U
|
||||
#define DBSC_V3M_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_V3M_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_V3M_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_V3M_DBCAM0CTRL0 0xE6790940U
|
||||
#define DBSC_V3M_DBCAM0STAT0 0xE6790980U
|
||||
#define DBSC_V3M_DBCAM1STAT0 0xE6790990U
|
||||
#define DBSC_V3M_DBBCAMSWAP 0xE67909F0U
|
||||
#define DBSC_V3M_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_V3M_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_V3M_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_V3M_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_V3M_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_V3M_DBSCHRW1 0xE6791024U
|
||||
#define DBSC_V3M_DBSCHQOS00 0xE6791030U
|
||||
#define DBSC_V3M_DBSCHQOS01 0xE6791034U
|
||||
#define DBSC_V3M_DBSCHQOS02 0xE6791038U
|
||||
#define DBSC_V3M_DBSCHQOS03 0xE679103CU
|
||||
#define DBSC_V3M_DBSCHQOS10 0xE6791040U
|
||||
#define DBSC_V3M_DBSCHQOS11 0xE6791044U
|
||||
#define DBSC_V3M_DBSCHQOS12 0xE6791048U
|
||||
#define DBSC_V3M_DBSCHQOS13 0xE679104CU
|
||||
#define DBSC_V3M_DBSCHQOS20 0xE6791050U
|
||||
#define DBSC_V3M_DBSCHQOS21 0xE6791054U
|
||||
#define DBSC_V3M_DBSCHQOS22 0xE6791058U
|
||||
#define DBSC_V3M_DBSCHQOS23 0xE679105CU
|
||||
#define DBSC_V3M_DBSCHQOS30 0xE6791060U
|
||||
#define DBSC_V3M_DBSCHQOS31 0xE6791064U
|
||||
#define DBSC_V3M_DBSCHQOS32 0xE6791068U
|
||||
#define DBSC_V3M_DBSCHQOS33 0xE679106CU
|
||||
#define DBSC_V3M_DBSCHQOS40 0xE6791070U
|
||||
#define DBSC_V3M_DBSCHQOS41 0xE6791074U
|
||||
#define DBSC_V3M_DBSCHQOS42 0xE6791078U
|
||||
#define DBSC_V3M_DBSCHQOS43 0xE679107CU
|
||||
#define DBSC_V3M_DBSCHQOS50 0xE6791080U
|
||||
#define DBSC_V3M_DBSCHQOS51 0xE6791084U
|
||||
#define DBSC_V3M_DBSCHQOS52 0xE6791088U
|
||||
#define DBSC_V3M_DBSCHQOS53 0xE679108CU
|
||||
#define DBSC_V3M_DBSCHQOS60 0xE6791090U
|
||||
#define DBSC_V3M_DBSCHQOS61 0xE6791094U
|
||||
#define DBSC_V3M_DBSCHQOS62 0xE6791098U
|
||||
#define DBSC_V3M_DBSCHQOS63 0xE679109CU
|
||||
#define DBSC_V3M_DBSCHQOS70 0xE67910A0U
|
||||
#define DBSC_V3M_DBSCHQOS71 0xE67910A4U
|
||||
#define DBSC_V3M_DBSCHQOS72 0xE67910A8U
|
||||
#define DBSC_V3M_DBSCHQOS73 0xE67910ACU
|
||||
#define DBSC_V3M_DBSCHQOS80 0xE67910B0U
|
||||
#define DBSC_V3M_DBSCHQOS81 0xE67910B4U
|
||||
#define DBSC_V3M_DBSCHQOS82 0xE67910B8U
|
||||
#define DBSC_V3M_DBSCHQOS83 0xE67910BCU
|
||||
#define DBSC_V3M_DBSCHQOS90 0xE67910C0U
|
||||
#define DBSC_V3M_DBSCHQOS91 0xE67910C4U
|
||||
#define DBSC_V3M_DBSCHQOS92 0xE67910C8U
|
||||
#define DBSC_V3M_DBSCHQOS93 0xE67910CCU
|
||||
#define DBSC_V3M_DBSCHQOS100 0xE67910D0U
|
||||
#define DBSC_V3M_DBSCHQOS101 0xE67910D4U
|
||||
#define DBSC_V3M_DBSCHQOS102 0xE67910D8U
|
||||
#define DBSC_V3M_DBSCHQOS103 0xE67910DCU
|
||||
#define DBSC_V3M_DBSCHQOS110 0xE67910E0U
|
||||
#define DBSC_V3M_DBSCHQOS111 0xE67910E4U
|
||||
#define DBSC_V3M_DBSCHQOS112 0xE67910E8U
|
||||
#define DBSC_V3M_DBSCHQOS113 0xE67910ECU
|
||||
#define DBSC_V3M_DBSCHQOS120 0xE67910F0U
|
||||
#define DBSC_V3M_DBSCHQOS121 0xE67910F4U
|
||||
#define DBSC_V3M_DBSCHQOS122 0xE67910F8U
|
||||
#define DBSC_V3M_DBSCHQOS123 0xE67910FCU
|
||||
#define DBSC_V3M_DBSCHQOS130 0xE6791100U
|
||||
#define DBSC_V3M_DBSCHQOS131 0xE6791104U
|
||||
#define DBSC_V3M_DBSCHQOS132 0xE6791108U
|
||||
#define DBSC_V3M_DBSCHQOS133 0xE679110CU
|
||||
#define DBSC_V3M_DBSCHQOS140 0xE6791110U
|
||||
#define DBSC_V3M_DBSCHQOS141 0xE6791114U
|
||||
#define DBSC_V3M_DBSCHQOS142 0xE6791118U
|
||||
#define DBSC_V3M_DBSCHQOS143 0xE679111CU
|
||||
#define DBSC_V3M_DBSCHQOS150 0xE6791120U
|
||||
#define DBSC_V3M_DBSCHQOS151 0xE6791124U
|
||||
#define DBSC_V3M_DBSCHQOS152 0xE6791128U
|
||||
#define DBSC_V3M_DBSCHQOS153 0xE679112CU
|
||||
#define DBSC_V3M_SCFCTST0 0xE6791700U
|
||||
#define DBSC_V3M_SCFCTST1 0xE6791708U
|
||||
#define DBSC_V3M_SCFCTST2 0xE679170CU
|
||||
#define DBSC_V3M_DBMRRDR0 0xE6791800U
|
||||
#define DBSC_V3M_DBMRRDR1 0xE6791804U
|
||||
#define DBSC_V3M_DBMRRDR2 0xE6791808U
|
||||
#define DBSC_V3M_DBMRRDR3 0xE679180CU
|
||||
#define DBSC_V3M_DBMRRDR4 0xE6791810U
|
||||
#define DBSC_V3M_DBMRRDR5 0xE6791814U
|
||||
#define DBSC_V3M_DBMRRDR6 0xE6791818U
|
||||
#define DBSC_V3M_DBMRRDR7 0xE679181CU
|
||||
#define DBSC_V3M_DBDTMP0 0xE6791820U
|
||||
#define DBSC_V3M_DBDTMP1 0xE6791824U
|
||||
#define DBSC_V3M_DBDTMP2 0xE6791828U
|
||||
#define DBSC_V3M_DBDTMP3 0xE679182CU
|
||||
#define DBSC_V3M_DBDTMP4 0xE6791830U
|
||||
#define DBSC_V3M_DBDTMP5 0xE6791834U
|
||||
#define DBSC_V3M_DBDTMP6 0xE6791838U
|
||||
#define DBSC_V3M_DBDTMP7 0xE679183CU
|
||||
#define DBSC_V3M_DBDQSOSC00 0xE6791840U
|
||||
#define DBSC_V3M_DBDQSOSC01 0xE6791844U
|
||||
#define DBSC_V3M_DBDQSOSC10 0xE6791848U
|
||||
#define DBSC_V3M_DBDQSOSC11 0xE679184CU
|
||||
#define DBSC_V3M_DBDQSOSC20 0xE6791850U
|
||||
#define DBSC_V3M_DBDQSOSC21 0xE6791854U
|
||||
#define DBSC_V3M_DBDQSOSC30 0xE6791858U
|
||||
#define DBSC_V3M_DBDQSOSC31 0xE679185CU
|
||||
#define DBSC_V3M_DBDQSOSC40 0xE6791860U
|
||||
#define DBSC_V3M_DBDQSOSC41 0xE6791864U
|
||||
#define DBSC_V3M_DBDQSOSC50 0xE6791868U
|
||||
#define DBSC_V3M_DBDQSOSC51 0xE679186CU
|
||||
#define DBSC_V3M_DBDQSOSC60 0xE6791870U
|
||||
#define DBSC_V3M_DBDQSOSC61 0xE6791874U
|
||||
#define DBSC_V3M_DBDQSOSC70 0xE6791878U
|
||||
#define DBSC_V3M_DBDQSOSC71 0xE679187CU
|
||||
#define DBSC_V3M_DBOSCTHH00 0xE6791880U
|
||||
#define DBSC_V3M_DBOSCTHH01 0xE6791884U
|
||||
#define DBSC_V3M_DBOSCTHH10 0xE6791888U
|
||||
#define DBSC_V3M_DBOSCTHH11 0xE679188CU
|
||||
#define DBSC_V3M_DBOSCTHH20 0xE6791890U
|
||||
#define DBSC_V3M_DBOSCTHH21 0xE6791894U
|
||||
#define DBSC_V3M_DBOSCTHH30 0xE6791898U
|
||||
#define DBSC_V3M_DBOSCTHH31 0xE679189CU
|
||||
#define DBSC_V3M_DBOSCTHH40 0xE67918A0U
|
||||
#define DBSC_V3M_DBOSCTHH41 0xE67918A4U
|
||||
#define DBSC_V3M_DBOSCTHH50 0xE67918A8U
|
||||
#define DBSC_V3M_DBOSCTHH51 0xE67918ACU
|
||||
#define DBSC_V3M_DBOSCTHH60 0xE67918B0U
|
||||
#define DBSC_V3M_DBOSCTHH61 0xE67918B4U
|
||||
#define DBSC_V3M_DBOSCTHH70 0xE67918B8U
|
||||
#define DBSC_V3M_DBOSCTHH71 0xE67918BCU
|
||||
#define DBSC_V3M_DBOSCTHL00 0xE67918C0U
|
||||
#define DBSC_V3M_DBOSCTHL01 0xE67918C4U
|
||||
#define DBSC_V3M_DBOSCTHL10 0xE67918C8U
|
||||
#define DBSC_V3M_DBOSCTHL11 0xE67918CCU
|
||||
#define DBSC_V3M_DBOSCTHL20 0xE67918D0U
|
||||
#define DBSC_V3M_DBOSCTHL21 0xE67918D4U
|
||||
#define DBSC_V3M_DBOSCTHL30 0xE67918D8U
|
||||
#define DBSC_V3M_DBOSCTHL31 0xE67918DCU
|
||||
#define DBSC_V3M_DBOSCTHL40 0xE67918E0U
|
||||
#define DBSC_V3M_DBOSCTHL41 0xE67918E4U
|
||||
#define DBSC_V3M_DBOSCTHL50 0xE67918E8U
|
||||
#define DBSC_V3M_DBOSCTHL51 0xE67918ECU
|
||||
#define DBSC_V3M_DBOSCTHL60 0xE67918F0U
|
||||
#define DBSC_V3M_DBOSCTHL61 0xE67918F4U
|
||||
#define DBSC_V3M_DBOSCTHL70 0xE67918F8U
|
||||
#define DBSC_V3M_DBOSCTHL71 0xE67918FCU
|
||||
#define DBSC_V3M_DBMEMSWAPCONF0 0xE6792000U
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/
|
||||
|
|
@ -6,6 +6,8 @@
|
|||
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
|
||||
else
|
||||
else ifeq (${RCAR_LSI},${RCAR_D3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
|
||||
else
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,339 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "boot_init_dram.h"
|
||||
#include "boot_init_dram_regdef_v3m.h"
|
||||
|
||||
static void WriteReg_32(uintptr_t a, uint32_t v)
|
||||
{
|
||||
*(volatile uint32_t*)a = v;
|
||||
}
|
||||
|
||||
static uint32_t ReadReg_32(uintptr_t a)
|
||||
{
|
||||
uint32_t w = *(volatile uint32_t*)a;
|
||||
return w;
|
||||
}
|
||||
|
||||
static uint32_t init_ddr_v3m_1600(void)
|
||||
{
|
||||
// last modified 2016.12.16
|
||||
|
||||
uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
|
||||
WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
|
||||
#if RCAR_DRAM_DDR3L_MEMCONF == 0
|
||||
WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
|
||||
#else
|
||||
WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
|
||||
#endif
|
||||
WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
|
||||
WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
|
||||
WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
|
||||
WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
|
||||
WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
|
||||
WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
|
||||
WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
|
||||
WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
|
||||
WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
|
||||
WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
|
||||
WriteReg_32(DBSC_V3M_DBTR11,0x0000000B);
|
||||
WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
|
||||
WriteReg_32(DBSC_V3M_DBTR13,0x01180118);
|
||||
WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
|
||||
WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
|
||||
WriteReg_32(DBSC_V3M_DBTR16,0x071D0305);
|
||||
WriteReg_32(DBSC_V3M_DBTR17,0x040C0010);
|
||||
WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
|
||||
WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
|
||||
WriteReg_32(DBSC_V3M_DBTR20,0x02000120);
|
||||
WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
|
||||
WriteReg_32(DBSC_V3M_DBBL,0x00000000);
|
||||
WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010);
|
||||
WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000);
|
||||
WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f);
|
||||
WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010);
|
||||
WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200);
|
||||
WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080);
|
||||
WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040);
|
||||
WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
|
||||
WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04);
|
||||
WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4);
|
||||
WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003);
|
||||
WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080);
|
||||
WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
|
||||
WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
|
||||
WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
|
||||
while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
|
||||
WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i<4; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
|
||||
RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
|
||||
if ( RegVal_R6 > 0 )
|
||||
{
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
|
||||
} else {
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
|
||||
}
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
for (uint32_t i = 0; i < 4; i++)
|
||||
{
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
|
||||
RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
|
||||
RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
|
||||
RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
|
||||
RegVal_R12 = (RegVal_R5 >> 2);
|
||||
if (RegVal_R6 - RegVal_R12 > 0)
|
||||
{
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
|
||||
}
|
||||
else
|
||||
{
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
|
||||
RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
|
||||
}
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
|
||||
while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
|
||||
while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );
|
||||
WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
|
||||
WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);
|
||||
|
||||
WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
|
||||
WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001);
|
||||
WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E);
|
||||
WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860);
|
||||
WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);
|
||||
WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
|
||||
WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBACEN,0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
|
||||
WriteReg_32(0xE67F0024, 0x00000001);
|
||||
WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int32_t rcar_dram_init(void)
|
||||
{
|
||||
return init_ddr_v3m_1600() ? INITDRAM_OK : INITDRAM_NG;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_V3M_H__
|
||||
#define PFC_INIT_V3M_H__
|
||||
|
||||
void pfc_init_v3m(void);
|
||||
|
||||
#endif /* PFC_INIT_V3M_H__ */
|
||||
|
|
@ -9,6 +9,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
|
|||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
|
||||
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
|
|
@ -25,6 +26,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
|
|||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
|
||||
endif
|
||||
|
|
@ -51,6 +55,9 @@ else
|
|||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include "H3/pfc_init_h3_v2.h"
|
||||
#include "M3/pfc_init_m3.h"
|
||||
#include "M3N/pfc_init_m3n.h"
|
||||
#include "V3M/pfc_init_v3m.h"
|
||||
#endif
|
||||
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) /* H3 */
|
||||
#include "H3/pfc_init_h3_v1.h"
|
||||
|
|
@ -26,6 +27,9 @@
|
|||
#if RCAR_LSI == RCAR_M3N /* M3N */
|
||||
#include "M3N/pfc_init_m3n.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_V3M /* V3M */
|
||||
#include "V3M/pfc_init_v3m.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_E3 /* E3 */
|
||||
#include "E3/pfc_init_e3.h"
|
||||
#endif
|
||||
|
|
@ -39,6 +43,7 @@
|
|||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
|
||||
|
|
@ -83,6 +88,9 @@ void rcar_pfc_init(void)
|
|||
case RCAR_PRODUCT_M3N:
|
||||
pfc_init_m3n();
|
||||
break;
|
||||
case RCAR_PRODUCT_V3M:
|
||||
pfc_init_v3m();
|
||||
break;
|
||||
default:
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
break;
|
||||
|
|
@ -119,6 +127,13 @@ void rcar_pfc_init(void)
|
|||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
pfc_init_m3n();
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_V3M:
|
||||
#if RCAR_LSI != RCAR_V3M
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
pfc_init_v3m();
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_E3:
|
||||
|
|
@ -173,6 +188,11 @@ void rcar_pfc_init(void)
|
|||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_m3n();
|
||||
#elif RCAR_LSI == RCAR_V3M /* V3M */
|
||||
if ((PRR_PRODUCT_V3M) != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_v3m();
|
||||
#elif RCAR_LSI == RCAR_E3 /* E3 */
|
||||
if ((PRR_PRODUCT_E3) != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <common/debug.h>
|
||||
#include "qos_init_v3m.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.01"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
|
||||
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t*)addr = value;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t*)addr = value;
|
||||
}
|
||||
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x000000000000FFFFU},
|
||||
{0x0008U, 0x000000000000FFFFU},
|
||||
{0x0010U, 0x000000000000FFFFU},
|
||||
{0x0018U, 0x000000000000FFFFU},
|
||||
{0x0020U, 0x001414090000FFFFU},
|
||||
{0x0028U, 0x000C00000000FFFFU},
|
||||
{0x0030U, 0x001008040000FFFFU},
|
||||
{0x0038U, 0x001004040000FFFFU},
|
||||
{0x0040U, 0x001004040000FFFFU},
|
||||
{0x0048U, 0x000000000000FFFFU},
|
||||
{0x0050U, 0x001004040000FFFFU},
|
||||
{0x0058U, 0x001004040000FFFFU},
|
||||
{0x0060U, 0x000000000000FFFFU},
|
||||
{0x0068U, 0x001404040000FFFFU},
|
||||
{0x0070U, 0x001008030000FFFFU},
|
||||
{0x0078U, 0x001004030000FFFFU},
|
||||
{0x0080U, 0x001004030000FFFFU},
|
||||
{0x0088U, 0x000000000000FFFFU},
|
||||
{0x0090U, 0x001004040000FFFFU},
|
||||
{0x0098U, 0x001004040000FFFFU},
|
||||
{0x00A0U, 0x000000000000FFFFU},
|
||||
{0x00A8U, 0x000000000000FFFFU},
|
||||
{0x00B0U, 0x000000000000FFFFU},
|
||||
{0x00B8U, 0x000000000000FFFFU},
|
||||
{0x00C0U, 0x000000000000FFFFU},
|
||||
{0x00C8U, 0x000000000000FFFFU},
|
||||
{0x00D0U, 0x000000000000FFFFU},
|
||||
{0x00D8U, 0x000000000000FFFFU},
|
||||
{0x00E0U, 0x001404020000FFFFU},
|
||||
{0x00E8U, 0x000000000000FFFFU},
|
||||
{0x00F0U, 0x000000000000FFFFU},
|
||||
{0x00F8U, 0x000000000000FFFFU},
|
||||
{0x0100U, 0x000000000000FFFFU},
|
||||
{0x0108U, 0x000C04020000FFFFU},
|
||||
{0x0110U, 0x000000000000FFFFU},
|
||||
{0x0118U, 0x001404020000FFFFU},
|
||||
{0x0120U, 0x000000000000FFFFU},
|
||||
{0x0128U, 0x000000000000FFFFU},
|
||||
{0x0130U, 0x000000000000FFFFU},
|
||||
{0x0138U, 0x000000000000FFFFU},
|
||||
{0x0140U, 0x000000000000FFFFU},
|
||||
{0x0148U, 0x000000000000FFFFU},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x00100020447FFC01U},
|
||||
{0x0008U, 0x00100020447FFC01U},
|
||||
{0x0010U, 0x00100040447FFC01U},
|
||||
{0x0018U, 0x00100040447FFC01U},
|
||||
{0x0020U, 0x0000000000000000U},
|
||||
{0x0028U, 0x0000000000000000U},
|
||||
{0x0030U, 0x0000000000000000U},
|
||||
{0x0038U, 0x0000000000000000U},
|
||||
{0x0040U, 0x0000000000000000U},
|
||||
{0x0048U, 0x0000000000000000U},
|
||||
{0x0050U, 0x0000000000000000U},
|
||||
{0x0058U, 0x0000000000000000U},
|
||||
{0x0060U, 0x0000000000000000U},
|
||||
{0x0068U, 0x0000000000000000U},
|
||||
{0x0070U, 0x0000000000000000U},
|
||||
{0x0078U, 0x0000000000000000U},
|
||||
{0x0080U, 0x0000000000000000U},
|
||||
{0x0088U, 0x0000000000000000U},
|
||||
{0x0090U, 0x0000000000000000U},
|
||||
{0x0098U, 0x0000000000000000U},
|
||||
{0x00A0U, 0x00100010447FFC01U},
|
||||
{0x00A8U, 0x00100010447FFC01U},
|
||||
{0x00B0U, 0x00100010447FFC01U},
|
||||
{0x00B8U, 0x00100010447FFC01U},
|
||||
{0x00C0U, 0x00100010447FFC01U},
|
||||
{0x00C8U, 0x00100010447FFC01U},
|
||||
{0x00D0U, 0x0000000000000000U},
|
||||
{0x00D8U, 0x00100010447FFC01U},
|
||||
{0x00E0U, 0x0000000000000000U},
|
||||
{0x00E8U, 0x00100010447FFC01U},
|
||||
{0x00F0U, 0x00100010447FFC01U},
|
||||
{0x00F8U, 0x00100010447FFC01U},
|
||||
{0x0100U, 0x00100010447FFC01U},
|
||||
{0x0108U, 0x0000000000000000U},
|
||||
{0x0110U, 0x00100010447FFC01U},
|
||||
{0x0118U, 0x0000000000000000U},
|
||||
{0x0120U, 0x00100010447FFC01U},
|
||||
{0x0128U, 0x00100010447FFC01U},
|
||||
{0x0130U, 0x00100010447FFC01U},
|
||||
{0x0138U, 0x00100010447FFC01U},
|
||||
{0x0140U, 0x00100020447FFC01U},
|
||||
{0x0148U, 0x00100020447FFC01U},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
|
||||
/* BUFCAM settings */
|
||||
//DBSC_DBCAM0CNF0 not set
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
|
||||
//io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F003F); //dbschcnt0
|
||||
io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt0
|
||||
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
|
||||
io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1
|
||||
io_write_32(DBSC_SCFCTST0,0x180B1708);
|
||||
io_write_32(DBSC_SCFCTST1,0x0808070C);
|
||||
io_write_32(DBSC_SCFCTST2,0x012F1123);
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_1_0 not set
|
||||
//DBSC_DBSCHQOS_1_1 not set
|
||||
//DBSC_DBSCHQOS_1_2 not set
|
||||
//DBSC_DBSCHQOS_1_3 not set
|
||||
//DBSC_DBSCHQOS_2_0 not set
|
||||
//DBSC_DBSCHQOS_2_1 not set
|
||||
//DBSC_DBSCHQOS_2_2 not set
|
||||
//DBSC_DBSCHQOS_2_3 not set
|
||||
//DBSC_DBSCHQOS_3_0 not set
|
||||
//DBSC_DBSCHQOS_3_1 not set
|
||||
//DBSC_DBSCHQOS_3_2 not set
|
||||
//DBSC_DBSCHQOS_3_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_5_0 not set
|
||||
//DBSC_DBSCHQOS_5_1 not set
|
||||
//DBSC_DBSCHQOS_5_2 not set
|
||||
//DBSC_DBSCHQOS_5_3 not set
|
||||
//DBSC_DBSCHQOS_6_0 not set
|
||||
//DBSC_DBSCHQOS_6_1 not set
|
||||
//DBSC_DBSCHQOS_6_2 not set
|
||||
//DBSC_DBSCHQOS_6_3 not set
|
||||
//DBSC_DBSCHQOS_7_0 not set
|
||||
//DBSC_DBSCHQOS_7_1 not set
|
||||
//DBSC_DBSCHQOS_7_2 not set
|
||||
//DBSC_DBSCHQOS_7_3 not set
|
||||
//DBSC_DBSCHQOS_8_0 not set
|
||||
//DBSC_DBSCHQOS_8_1 not set
|
||||
//DBSC_DBSCHQOS_8_2 not set
|
||||
//DBSC_DBSCHQOS_8_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000);
|
||||
//DBSC_DBSCHQOS_10_0 not set
|
||||
//DBSC_DBSCHQOS_10_1 not set
|
||||
//DBSC_DBSCHQOS_10_2 not set
|
||||
//DBSC_DBSCHQOS_10_3 not set
|
||||
//DBSC_DBSCHQOS_11_0 not set
|
||||
//DBSC_DBSCHQOS_11_1 not set
|
||||
//DBSC_DBSCHQOS_11_2 not set
|
||||
//DBSC_DBSCHQOS_11_3 not set
|
||||
//DBSC_DBSCHQOS_12_0 not set
|
||||
//DBSC_DBSCHQOS_12_1 not set
|
||||
//DBSC_DBSCHQOS_12_2 not set
|
||||
//DBSC_DBSCHQOS_12_3 not set
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
|
||||
}
|
||||
|
||||
void qos_init_v3m(void)
|
||||
{
|
||||
return;
|
||||
|
||||
dbsc_setting();
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000020U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000004U);
|
||||
io_write_64(RALLOC_DANN, 0x0202020104040200U);
|
||||
io_write_32(RALLOC_DANT, 0x00201008U);
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000U);
|
||||
io_write_32(RALLOC_INSFC, 0x63C20001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT, 0x0305007DU);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* AXI-IF arbitration setting */
|
||||
io_write_32(DBSC_AXARB, 0x18010000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_V3M__
|
||||
#define QOS_INIT_H_V3M__
|
||||
|
||||
void qos_init_v3m(void);
|
||||
|
||||
#endif /* QOS_INIT_H_V3M__ */
|
||||
|
|
@ -14,6 +14,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
|
|||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
|
|
@ -32,6 +33,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
|
|||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
|
|
@ -83,6 +87,9 @@ else
|
|||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_V3M})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include "M3/qos_init_m3_v11.h"
|
||||
#include "M3/qos_init_m3_v30.h"
|
||||
#include "M3N/qos_init_m3n_v10.h"
|
||||
#include "V3M/qos_init_v3m.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_H3 /* H3 */
|
||||
#include "H3/qos_init_h3_v10.h"
|
||||
|
|
@ -38,6 +39,9 @@
|
|||
#if RCAR_LSI == RCAR_M3N /* M3N */
|
||||
#include "M3N/qos_init_m3n_v10.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_V3M /* V3M */
|
||||
#include "V3M/qos_init_v3m.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_E3 /* E3 */
|
||||
#include "E3/qos_init_e3_v10.h"
|
||||
#endif
|
||||
|
|
@ -51,6 +55,7 @@
|
|||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
|
||||
|
|
@ -60,7 +65,7 @@
|
|||
#define PRR_PRODUCT_21 (0x11U)
|
||||
#define PRR_PRODUCT_30 (0x20U)
|
||||
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
|
||||
|
||||
#define DRAM_CH_CNT 0x04
|
||||
uint32_t qos_init_ddr_ch;
|
||||
|
|
@ -85,7 +90,7 @@ uint8_t qos_init_ddr_phyvalid;
|
|||
void rcar_qos_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
|
||||
uint32_t i;
|
||||
|
||||
qos_init_ddr_ch = 0;
|
||||
|
|
@ -156,6 +161,19 @@ void rcar_qos_init(void)
|
|||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_V3M:
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
case PRR_PRODUCT_20:
|
||||
default:
|
||||
qos_init_v3m();
|
||||
break;
|
||||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_E3:
|
||||
|
|
@ -261,6 +279,13 @@ void rcar_qos_init(void)
|
|||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_m3n_v10();
|
||||
#elif RCAR_LSI == RCAR_V3M /* V3M */
|
||||
/* V3M Cut 10 or later */
|
||||
if ((PRR_PRODUCT_V3M)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_v3m();
|
||||
#elif RCAR_LSI == RCAR_D3 /* D3 */
|
||||
/* D3 Cut 10 or later */
|
||||
if ((PRR_PRODUCT_D3)
|
||||
|
|
@ -281,7 +306,7 @@ void rcar_qos_init(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
|
||||
uint32_t get_refperiod(void)
|
||||
{
|
||||
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,11 @@ static void bl2_realtime_cpg_init_m3n(void);
|
|||
static void bl2_system_cpg_init_m3n(void);
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
|
||||
static void bl2_realtime_cpg_init_v3m(void);
|
||||
static void bl2_system_cpg_init_v3m(void);
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
|
||||
static void bl2_realtime_cpg_init_e3(void);
|
||||
static void bl2_system_cpg_init_e3(void);
|
||||
|
|
@ -216,6 +221,38 @@ static void bl2_system_cpg_init_m3n(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
|
||||
static void bl2_realtime_cpg_init_v3m(void)
|
||||
{
|
||||
/* Realtime Module Stop Control Registers */
|
||||
cpg_write(RMSTPCR0, 0x00230000U);
|
||||
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
|
||||
cpg_write(RMSTPCR2, 0x14062FD8U);
|
||||
cpg_write(RMSTPCR3, 0xFFFFFFDFU);
|
||||
cpg_write(RMSTPCR4, 0x80000184U);
|
||||
cpg_write(RMSTPCR5, 0x83FFFFFFU);
|
||||
cpg_write(RMSTPCR6, 0xFFFFFFFFU);
|
||||
cpg_write(RMSTPCR7, 0xFFFFFFFFU);
|
||||
cpg_write(RMSTPCR8, 0x7FF3FFF4U);
|
||||
cpg_write(RMSTPCR9, 0xFFFFFFFEU);
|
||||
}
|
||||
|
||||
static void bl2_system_cpg_init_v3m(void)
|
||||
{
|
||||
/* System Module Stop Control Registers */
|
||||
cpg_write(SMSTPCR0, 0x00210000U);
|
||||
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
|
||||
cpg_write(SMSTPCR2, 0x340E2FDCU);
|
||||
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
|
||||
cpg_write(SMSTPCR4, 0x80000004U);
|
||||
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
|
||||
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
|
||||
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
|
||||
cpg_write(SMSTPCR8, 0x01F1FFF5U);
|
||||
cpg_write(SMSTPCR9, 0xFFFFFFFEU);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
|
||||
static void bl2_realtime_cpg_init_e3(void)
|
||||
{
|
||||
|
|
@ -310,6 +347,9 @@ void bl2_cpg_init(void)
|
|||
case RCAR_PRODUCT_M3N:
|
||||
bl2_realtime_cpg_init_m3n();
|
||||
break;
|
||||
case RCAR_PRODUCT_V3M:
|
||||
bl2_realtime_cpg_init_v3m();
|
||||
break;
|
||||
case RCAR_PRODUCT_E3:
|
||||
bl2_realtime_cpg_init_e3();
|
||||
break;
|
||||
|
|
@ -326,6 +366,8 @@ void bl2_cpg_init(void)
|
|||
bl2_realtime_cpg_init_m3();
|
||||
#elif RCAR_LSI == RCAR_M3N
|
||||
bl2_realtime_cpg_init_m3n();
|
||||
#elif RCAR_LSI == RCAR_V3M
|
||||
bl2_realtime_cpg_init_v3m();
|
||||
#elif RCAR_LSI == RCAR_E3
|
||||
bl2_realtime_cpg_init_e3();
|
||||
#elif RCAR_LSI == RCAR_D3
|
||||
|
|
@ -351,6 +393,9 @@ void bl2_system_cpg_init(void)
|
|||
case RCAR_PRODUCT_M3N:
|
||||
bl2_system_cpg_init_m3n();
|
||||
break;
|
||||
case RCAR_PRODUCT_V3M:
|
||||
bl2_system_cpg_init_v3m();
|
||||
break;
|
||||
case RCAR_PRODUCT_E3:
|
||||
bl2_system_cpg_init_e3();
|
||||
break;
|
||||
|
|
@ -367,6 +412,8 @@ void bl2_system_cpg_init(void)
|
|||
bl2_system_cpg_init_m3();
|
||||
#elif RCAR_LSI == RCAR_M3N
|
||||
bl2_system_cpg_init_m3n();
|
||||
#elif RCAR_LSI == RCAR_V3M
|
||||
bl2_system_cpg_init_v3m();
|
||||
#elif RCAR_LSI == RCAR_E3
|
||||
bl2_system_cpg_init_e3();
|
||||
#elif RCAR_LSI == RCAR_D3
|
||||
|
|
|
|||
|
|
@ -73,6 +73,9 @@ static void bl2_init_generic_timer(void);
|
|||
#elif RCAR_LSI == RCAR_M3N
|
||||
#define TARGET_PRODUCT RCAR_PRODUCT_M3N
|
||||
#define TARGET_NAME "R-Car M3N"
|
||||
#elif RCAR_LSI == RCAR_V3M
|
||||
#define TARGET_PRODUCT RCAR_PRODUCT_V3M
|
||||
#define TARGET_NAME "R-Car V3M"
|
||||
#elif RCAR_LSI == RCAR_E3
|
||||
#define TARGET_PRODUCT RCAR_PRODUCT_E3
|
||||
#define TARGET_NAME "R-Car E3"
|
||||
|
|
@ -80,7 +83,7 @@ static void bl2_init_generic_timer(void);
|
|||
#define TARGET_PRODUCT RCAR_PRODUCT_D3
|
||||
#define TARGET_NAME "R-Car D3"
|
||||
#elif RCAR_LSI == RCAR_AUTO
|
||||
#define TARGET_NAME "R-Car H3/M3/M3N"
|
||||
#define TARGET_NAME "R-Car H3/M3/M3N/V3M"
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
|
|
@ -431,6 +434,10 @@ static void bl2_populate_compatible_string(void *fdt)
|
|||
ret = fdt_setprop_string(fdt, 0, "compatible",
|
||||
"renesas,h3ulcb");
|
||||
break;
|
||||
case BOARD_EAGLE:
|
||||
ret = fdt_setprop_string(fdt, 0, "compatible",
|
||||
"renesas,eagle");
|
||||
break;
|
||||
case BOARD_EBISU:
|
||||
case BOARD_EBISU_4D:
|
||||
ret = fdt_setprop_string(fdt, 0, "compatible",
|
||||
|
|
@ -464,6 +471,10 @@ static void bl2_populate_compatible_string(void *fdt)
|
|||
ret = fdt_appendprop_string(fdt, 0, "compatible",
|
||||
"renesas,r8a77965");
|
||||
break;
|
||||
case RCAR_PRODUCT_V3M:
|
||||
ret = fdt_appendprop_string(fdt, 0, "compatible",
|
||||
"renesas,r8a77970");
|
||||
break;
|
||||
case RCAR_PRODUCT_E3:
|
||||
ret = fdt_appendprop_string(fdt, 0, "compatible",
|
||||
"renesas,r8a77990");
|
||||
|
|
@ -600,6 +611,11 @@ static void bl2_advertise_dram_size(uint32_t product)
|
|||
dram_config[1] = 0x80000000ULL;
|
||||
break;
|
||||
|
||||
case RCAR_PRODUCT_V3M:
|
||||
/* 1GB(512MBx2) */
|
||||
dram_config[1] = 0x40000000ULL;
|
||||
break;
|
||||
|
||||
case RCAR_PRODUCT_E3:
|
||||
#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
|
||||
/* 1GB(512MBx2) */
|
||||
|
|
@ -637,6 +653,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
|||
const char *product_m3 = "M3";
|
||||
const char *product_e3 = "E3";
|
||||
const char *product_d3 = "D3";
|
||||
const char *product_v3m = "V3M";
|
||||
const char *lcs_secure = "SE";
|
||||
const char *lcs_cm = "CM";
|
||||
const char *lcs_dm = "DM";
|
||||
|
|
@ -713,6 +730,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
|||
case RCAR_PRODUCT_M3N:
|
||||
str = product_m3n;
|
||||
break;
|
||||
case RCAR_PRODUCT_V3M:
|
||||
str = product_v3m;
|
||||
break;
|
||||
case RCAR_PRODUCT_E3:
|
||||
str = product_e3;
|
||||
break;
|
||||
|
|
@ -760,6 +780,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
|||
case BOARD_STARTER_KIT_PRE:
|
||||
case BOARD_EBISU_4D:
|
||||
case BOARD_DRAAK:
|
||||
case BOARD_EAGLE:
|
||||
break;
|
||||
default:
|
||||
type = BOARD_UNKNOWN;
|
||||
|
|
@ -972,6 +993,7 @@ void bl2_platform_setup(void)
|
|||
|
||||
static void bl2_init_generic_timer(void)
|
||||
{
|
||||
/* FIXME: V3M 16.666 MHz ? */
|
||||
#if RCAR_LSI == RCAR_D3
|
||||
uint32_t reg_cntfid = EXTAL_DRAAK;
|
||||
#elif RCAR_LSI == RCAR_E3
|
||||
|
|
|
|||
|
|
@ -109,10 +109,14 @@
|
|||
#define BL2_LIMIT U(0xE6360000)
|
||||
#endif
|
||||
|
||||
#define BL2_BASE U(0xE6304000)
|
||||
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
|
||||
#define BL2_BASE U(0xE6304000)
|
||||
#define BL2_IMAGE_LIMIT U(0xE6318000)
|
||||
#elif (RCAR_LSI == RCAR_V3M)
|
||||
#define BL2_BASE U(0xE6344000)
|
||||
#define BL2_IMAGE_LIMIT U(0xE636E800)
|
||||
#else
|
||||
#define BL2_BASE U(0xE6304000)
|
||||
#define BL2_IMAGE_LIMIT U(0xE632E800)
|
||||
#endif
|
||||
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
|
||||
|
|
|
|||
|
|
@ -151,6 +151,7 @@
|
|||
#define RCAR_CUT_MASK U(0x000000FF)
|
||||
#define RCAR_PRODUCT_H3 U(0x00004F00)
|
||||
#define RCAR_PRODUCT_M3 U(0x00005200)
|
||||
#define RCAR_PRODUCT_V3M U(0x00005400)
|
||||
#define RCAR_PRODUCT_M3N U(0x00005500)
|
||||
#define RCAR_PRODUCT_E3 U(0x00005700)
|
||||
#define RCAR_PRODUCT_D3 U(0x00005800)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ RCAR_M3N:=2
|
|||
RCAR_E3:=3
|
||||
RCAR_H3N:=4
|
||||
RCAR_D3:=5
|
||||
RCAR_V3M:=6
|
||||
RCAR_AUTO:=99
|
||||
$(eval $(call add_define,RCAR_H3))
|
||||
$(eval $(call add_define,RCAR_M3))
|
||||
|
|
@ -37,6 +38,7 @@ $(eval $(call add_define,RCAR_M3N))
|
|||
$(eval $(call add_define,RCAR_E3))
|
||||
$(eval $(call add_define,RCAR_H3N))
|
||||
$(eval $(call add_define,RCAR_D3))
|
||||
$(eval $(call add_define,RCAR_V3M))
|
||||
$(eval $(call add_define,RCAR_AUTO))
|
||||
RCAR_CUT_10:=0
|
||||
RCAR_CUT_11:=1
|
||||
|
|
@ -160,6 +162,22 @@ else
|
|||
endif
|
||||
$(eval $(call add_define,RCAR_LSI_CUT))
|
||||
endif
|
||||
else ifeq (${LSI},V3M)
|
||||
RCAR_LSI:=${RCAR_V3M}
|
||||
ifndef LSI_CUT
|
||||
# enable compatible function.
|
||||
RCAR_LSI_CUT_COMPAT := 1
|
||||
$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
|
||||
else
|
||||
# disable compatible function.
|
||||
ifeq (${LSI_CUT},10)
|
||||
RCAR_LSI_CUT:=0
|
||||
endif
|
||||
ifeq (${LSI_CUT},20)
|
||||
RCAR_LSI_CUT:=10
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LSI_CUT))
|
||||
endif
|
||||
else
|
||||
$(error "Error: ${LSI} is not supported.")
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue