Add workaround for ARM Cortex-A53 erratum 855873
ARM erratum 855873 applies to all Cortex-A53 CPUs. The recommended workaround is to promote "data cache clean" instructions to "data cache clean and invalidate" instructions. For core revisions of r0p3 and later this can be done by setting a bit in the CPUACTLR_EL1 register, so that hardware takes care of the promotion. As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3, we set the bit in firmware. Also we dump this register upon crashing to provide more debug information. Enable the workaround for the Juno boards. Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara
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3944adca59
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@ -60,6 +60,13 @@ For Cortex-A53, following errata build flags are defined :
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CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
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r0p4 and onwards, this errata is enabled by default in hardware.
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* `ERRATA_A53_855873`: This applies errata 855873 workaround to Cortex-A53
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CPUs. Though the erratum is present in every revision of the CPU,
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this workaround is only applied to CPUs from r0p3 onwards, which feature
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a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
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Earlier revisions of the CPU have other errata which require the same
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workaround in software, so they should be covered anyway.
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For Cortex-A57, following errata build flags are defined :
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* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57
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@ -67,6 +67,7 @@
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#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
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#define CPUACTLR_DTAH (1 << 24)
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#define CPUACTLR_ENDCCASCI (1 << 44)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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@ -129,6 +129,39 @@ func check_errata_disable_non_temporal_hint
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b cpu_rev_var_ls
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endfunc check_errata_disable_non_temporal_hint
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #855873.
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*
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* This applies only to revisions >= r0p3 of Cortex A53.
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a53_855873_wa
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/*
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* Compare x0 against revision r0p3 and higher
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*/
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mov x17, x30
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bl check_errata_855873
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cbz x0, 1f
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mrs x1, CPUACTLR_EL1
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orr x1, x1, #CPUACTLR_ENDCCASCI
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msr CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_855873_wa
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func check_errata_855873
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mov x1, #0x03
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b cpu_rev_var_hs
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endfunc check_errata_855873
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Shall clobber: x0-x19
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@ -150,6 +183,11 @@ func cortex_a53_reset_func
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bl a53_disable_non_temporal_hint
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#endif
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#if ERRATA_A53_855873
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mov x0, x18
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bl errata_a53_855873_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -238,6 +276,7 @@ func cortex_a53_errata_report
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*/
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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ldp x8, x30, [sp], #16
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ret
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@ -255,13 +294,15 @@ endfunc cortex_a53_errata_report
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*/
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.section .rodata.cortex_a53_regs, "aS"
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cortex_a53_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \
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"cpuactlr_el1", ""
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func cortex_a53_cpu_reg_dump
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adr x6, cortex_a53_regs
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mrs x8, CPUECTLR_EL1
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mrs x9, CPUMERRSR_EL1
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mrs x10, L2MERRSR_EL1
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mrs x11, CPUACTLR_EL1
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ret
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endfunc cortex_a53_cpu_reg_dump
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@ -234,6 +234,20 @@ func cpu_rev_var_ls
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ret
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endfunc cpu_rev_var_ls
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is higher than or same as a
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* given value, indicates that errata applies; otherwise not.
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*/
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.globl cpu_rev_var_hs
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func cpu_rev_var_hs
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, hs
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ret
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endfunc cpu_rev_var_hs
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#if REPORT_ERRATA
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/*
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* void print_errata_status(void);
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@ -66,6 +66,12 @@ ERRATA_A53_826319 ?=0
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# erratum workaround is enabled by default in hardware.
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ERRATA_A53_836870 ?=0
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# Flag to apply errata 855873 during reset. This errata applies to all
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# revisions of the Cortex A53 CPU, but this firmware workaround only works
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# for revisions r0p3 and higher. Earlier revisions are taken care
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# of by the rich OS.
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ERRATA_A53_855873 ?=0
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# Flag to apply erratum 806969 workaround during reset. This erratum applies
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# only to revision r0p0 of the Cortex A57 cpu.
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ERRATA_A57_806969 ?=0
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@ -106,6 +112,10 @@ $(eval $(call add_define,ERRATA_A53_826319))
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$(eval $(call assert_boolean,ERRATA_A53_836870))
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$(eval $(call add_define,ERRATA_A53_836870))
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# Process ERRATA_A53_855873 flag
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$(eval $(call assert_boolean,ERRATA_A53_855873))
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$(eval $(call add_define,ERRATA_A53_855873))
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# Process ERRATA_A57_806969 flag
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$(eval $(call assert_boolean,ERRATA_A57_806969))
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$(eval $(call add_define,ERRATA_A57_806969))
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@ -67,7 +67,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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${JUNO_INTERCONNECT_SOURCES} \
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${JUNO_SECURITY_SOURCES}
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# Enable workarounds for selected Cortex-A57 erratas.
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# Enable workarounds for selected Cortex-A53 and A57 erratas.
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ERRATA_A53_855873 := 1
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ERRATA_A57_806969 := 0
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ERRATA_A57_813419 := 1
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ERRATA_A57_813420 := 1
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