rcar_gen3: drivers: qos: Fix checkpatch issues
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id0f1e322b44562f9863e885583d89fbf47cab91b
This commit is contained in:
Marek Vasut
parent
5ea5c2b24d
commit
b784916485
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -7,98 +7,106 @@
|
|||
#ifndef QOS_COMMON_H
|
||||
#define QOS_COMMON_H
|
||||
|
||||
#define RCAR_REF_DEFAULT (0U)
|
||||
#define RCAR_REF_DEFAULT 0U
|
||||
|
||||
/* define used for get_refperiod. */
|
||||
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
|
||||
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
|
||||
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
|
||||
#define REFPERIOD_CYCLE /* unit:ns */ \
|
||||
((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
|
||||
#else /* REF option */
|
||||
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
|
||||
#define REFPERIOD_CYCLE /* unit:ns */ \
|
||||
((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
/* define used for E3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
|
||||
#define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */
|
||||
#else /* REF 7.8usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
|
||||
#define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define OPERATING_FREQ_E3 (266U) /* MHz */
|
||||
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
|
||||
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
|
||||
#define OPERATING_FREQ_E3 266U /* MHz */
|
||||
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
/* define used for M3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
/* define used for H3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
/* define used for H3 Cut 30 */
|
||||
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
|
||||
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_H3N)
|
||||
/* define used for H3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
/* define used for M3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */
|
||||
#define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
|
||||
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U)
|
||||
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
#endif
|
||||
|
||||
#define OPERATING_FREQ (400U) /* MHz */
|
||||
#define BASE_SUB_SLOT_NUM (0x6U)
|
||||
#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
|
||||
#define OPERATING_FREQ 400U /* MHz */
|
||||
#define BASE_SUB_SLOT_NUM 0x6U
|
||||
#define SUB_SLOT_CYCLE 0x7EU /* 126 */
|
||||
|
||||
#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
|
||||
((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
|
||||
|
||||
#define SL_INIT_REFFSSLOT (0x3U << 24U)
|
||||
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
|
||||
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
|
||||
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -50,42 +50,41 @@
|
|||
#endif
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
|
||||
#define PRR_PRODUCT_10 (0x00U)
|
||||
#define PRR_PRODUCT_11 (0x01U)
|
||||
#define PRR_PRODUCT_20 (0x10U)
|
||||
#define PRR_PRODUCT_21 (0x11U)
|
||||
#define PRR_PRODUCT_30 (0x20U)
|
||||
#define PRR 0xFFF00044U
|
||||
#define PRR_PRODUCT_MASK 0x00007F00U
|
||||
#define PRR_CUT_MASK 0x000000FFU
|
||||
#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */
|
||||
#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
|
||||
#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
|
||||
#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
|
||||
#define PRR_PRODUCT_10 0x00U
|
||||
#define PRR_PRODUCT_11 0x01U
|
||||
#define PRR_PRODUCT_20 0x10U
|
||||
#define PRR_PRODUCT_21 0x11U
|
||||
#define PRR_PRODUCT_30 0x20U
|
||||
|
||||
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
|
||||
|
||||
#define DRAM_CH_CNT 0x04
|
||||
uint32_t qos_init_ddr_ch;
|
||||
uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
#endif
|
||||
|
||||
#define PRR_PRODUCT_ERR(reg) \
|
||||
do{ \
|
||||
do { \
|
||||
ERROR("LSI Product ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
"initialize not supported.\n", reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
} while (0)
|
||||
|
||||
#define PRR_CUT_ERR(reg) \
|
||||
do{ \
|
||||
do { \
|
||||
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
"initialize not supported.\n", reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
} while (0)
|
||||
|
||||
void rcar_qos_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -7,127 +7,127 @@
|
|||
#ifndef QOS_REG_H
|
||||
#define QOS_REG_H
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
#define RCAR_QOS_NONE 3U
|
||||
#define RCAR_QOS_TYPE_DEFAULT 0U
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
#define RCAR_DRAM_SPLIT_LINEAR 0U
|
||||
#define RCAR_DRAM_SPLIT_4CH 1U
|
||||
#define RCAR_DRAM_SPLIT_2CH 2U
|
||||
#define RCAR_DRAM_SPLIT_AUTO 3U
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
|
||||
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
#define DBSC_BASE 0xE6790000U
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
|
||||
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define AXI_MMCR (AXI_BASE + 0x0300U)
|
||||
#define AXI_BASE 0xE6784000U
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define AXI_MMCR (AXI_BASE + 0x0300U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP 0x0CU
|
||||
|
||||
#define AXI_TR3CR (0xE67D100CU)
|
||||
#define AXI_TR4CR (0xE67D1014U)
|
||||
#define AXI_TR3CR 0xE67D100CU
|
||||
#define AXI_TR4CR 0xE67D1014U
|
||||
|
||||
#define QOS_BASE0 (0xE67E0000U)
|
||||
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
|
||||
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
|
||||
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
|
||||
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
|
||||
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
|
||||
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
|
||||
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
|
||||
#define QOS_BASE0 0xE67E0000U
|
||||
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
|
||||
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
|
||||
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
|
||||
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
|
||||
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
|
||||
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
|
||||
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
|
||||
|
||||
#define QOS_BASE1 (0xE67F0000U)
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
|
||||
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
#define QOS_BASE1 0xE67F0000U
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
|
||||
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
#define GPU_ACT_GRD (0xFD820808U)
|
||||
#define GPU_ACT0 (0xFD820800U)
|
||||
#define GPU_ACT1 (0xFD821800U)
|
||||
#define GPU_ACT2 (0xFD822800U)
|
||||
#define GPU_ACT3 (0xFD823800U)
|
||||
#define GPU_ACT4 (0xFD824800U)
|
||||
#define GPU_ACT5 (0xFD825800U)
|
||||
#define GPU_ACT6 (0xFD826800U)
|
||||
#define GPU_ACT7 (0xFD827800U)
|
||||
#define GPU_ACT_GRD 0xFD820808U
|
||||
#define GPU_ACT0 0xFD820800U
|
||||
#define GPU_ACT1 0xFD821800U
|
||||
#define GPU_ACT2 0xFD822800U
|
||||
#define GPU_ACT3 0xFD823800U
|
||||
#define GPU_ACT4 0xFD824800U
|
||||
#define GPU_ACT5 0xFD825800U
|
||||
#define GPU_ACT6 0xFD826800U
|
||||
#define GPU_ACT7 0xFD827800U
|
||||
|
||||
#define RT_ACT0 (0xFFC50800U)
|
||||
#define RT_ACT1 (0xFFC51800U)
|
||||
#define RT_ACT0 0xFFC50800U
|
||||
#define RT_ACT1 0xFFC51800U
|
||||
|
||||
#define CPU_ACT0 (0xF1300800U)
|
||||
#define CPU_ACT1 (0xF1340800U)
|
||||
#define CPU_ACT2 (0xF1380800U)
|
||||
#define CPU_ACT3 (0xF13C0800U)
|
||||
#define CPU_ACT0 0xF1300800U
|
||||
#define CPU_ACT1 0xF1340800U
|
||||
#define CPU_ACT2 0xF1380800U
|
||||
#define CPU_ACT3 0xF13C0800U
|
||||
|
||||
#define RCAR_REWT_TRAINING_DISABLE (0U)
|
||||
#define RCAR_REWT_TRAINING_ENABLE (1U)
|
||||
#define RCAR_REWT_TRAINING_DISABLE 0U
|
||||
#define RCAR_REWT_TRAINING_ENABLE 1U
|
||||
|
||||
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
|
||||
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
|
||||
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
|
||||
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
|
||||
|
||||
#endif /* QOS_REG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue