Merge changes from topic "erratas" into integration
* changes: errata: workaround for Neoverse N2 erratum 2025414 errata: workaround for Neoverse N2 erratum 2067956
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
b7942a91b8
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@ -381,6 +381,14 @@ For Cortex-A710, the following errata build flags are defined :
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Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
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r2p0 of the CPU. It is still open.
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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DSU Errata Workarounds
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----------------------
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -21,10 +21,17 @@
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -61,9 +61,62 @@ func check_errata_2002655
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b cpu_rev_var_ls
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endfunc check_errata_2002655
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/* -------------------------------------------------
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/* ---------------------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2067956.
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* This applies to revision r0p0 of Neoverse N2 and is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------
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*/
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func errata_n2_2067956_wa
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/* Compare x0 against revision r0p0 */
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mov x17, x30
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bl check_errata_2067956
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cbz x0, 1f
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
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msr NEOVERSE_N2_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2067956_wa
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func check_errata_2067956
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2067956
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/* ---------------------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2025414.
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* This applies to revision r0p0 of Neoverse N2 and is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------
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*/
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func errata_n2_2025414_wa
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/* Compare x0 against revision r0p0 */
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mov x17, x30
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bl check_errata_2025414
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cbz x0, 1f
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mrs x1, NEOVERSE_N2_CPUECTLR_EL1
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orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
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msr NEOVERSE_N2_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2025414_wa
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func check_errata_2025414
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2025414
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/* -------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------------
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* -------------------------------------------
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*/
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func neoverse_n2_reset_func
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mov x19, x30
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@ -81,6 +134,16 @@ func neoverse_n2_reset_func
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orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
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msr NEOVERSE_N2_CPUACTLR2_EL1, x0
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#if ERRATA_N2_2067956
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mov x0, x18
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bl errata_n2_2067956_wa
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#endif
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#if ERRATA_N2_2025414
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mov x0, x18
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bl errata_n2_2025414_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, cptr_el3
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@ -97,9 +160,9 @@ func neoverse_n2_reset_func
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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mrs x0, NEOVERSE_N2_CPUECTLR_EL1
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orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
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msr NEOVERSE_N2_CPUECTLR_EL1, x0
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mrs x0, NEOVERSE_N2_CPUECTLR_EL1
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orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
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msr NEOVERSE_N2_CPUECTLR_EL1, x0
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#endif
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bl cpu_get_rev_var
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@ -111,14 +174,14 @@ func neoverse_n2_reset_func
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#endif
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isb
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ret x19
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ret x19
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endfunc neoverse_n2_reset_func
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func neoverse_n2_core_pwr_dwn
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/* ---------------------------------------------
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* No need to do cache maintenance here.
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* ---------------------------------------------
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* ---------------------------------------------------
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*/
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mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
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@ -142,6 +205,8 @@ func neoverse_n2_errata_report
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* checking functions of each errata.
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*/
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report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
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report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
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report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
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ldp x8, x30, [sp], #16
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ret
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@ -425,6 +425,14 @@ ERRATA_A710_1987031 ?=0
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# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2081180 ?=0
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# Flag to apply erratum 2067956 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2067956 ?=0
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# Flag to apply erratum 2025414 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2025414 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -782,6 +790,14 @@ $(eval $(call add_define,ERRATA_A710_1987031))
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$(eval $(call assert_boolean,ERRATA_A710_2081180))
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$(eval $(call add_define,ERRATA_A710_2081180))
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# Process ERRATA_N2_2067956 flag
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$(eval $(call assert_boolean,ERRATA_N2_2067956))
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$(eval $(call add_define,ERRATA_N2_2067956))
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# Process ERRATA_N2_2025414 flag
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$(eval $(call assert_boolean,ERRATA_N2_2025414))
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$(eval $(call add_define,ERRATA_N2_2025414))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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