refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes
COMPHY register addresses are defined twice - once for indirect access, where the constants are of the form COMPHY_<register_name> - once for direct access, with constants of the form <register_name>_ADDR But sometimes the first case also has this _ADDR suffix (and other times not). Drop it from those places to unify how we define these registers. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: Ibf95be8ade231d0e42258f40614a5f0974d280bd
This commit is contained in:
Marek Behún
parent
b3491336e0
commit
b7b0575d12
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@ -450,7 +450,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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*/
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data = 0;
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mask = PHY_REF_CLK_SEL;
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reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask);
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reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0, sd_ip_addr), data, mask);
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/*
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* 9. Set correct reference clock frequency in COMPHY register
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@ -646,39 +646,38 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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*/
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mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
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CFG_TX_ALIGN_POS_MASK;
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usb3_reg_set(reg_base, COMPHY_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
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mask);
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usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask);
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/*
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* 2. Set BIT0: enable transmitter in high impedance mode
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* Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
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* Set BIT6: Tx detect Rx at HiZ mode
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* Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
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* together with bit 0 of COMPHY_LANE_CFG0_ADDR register
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* together with bit 0 of COMPHY_LANE_CFG0 register
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*/
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mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
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TX_ELEC_IDLE_MODE_EN;
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data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
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usb3_reg_set(reg_base, COMPHY_LANE_CFG1_ADDR, data, mask);
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usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask);
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/*
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* 3. Set Spread Spectrum Clock Enabled
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*/
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usb3_reg_set(reg_base, COMPHY_LANE_CFG4_ADDR,
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usb3_reg_set(reg_base, COMPHY_LANE_CFG4,
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
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/*
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* 4. Set Override Margining Controls From the MAC:
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* Use margining signals from lane configuration
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*/
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usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL_ADDR,
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usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL,
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
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/*
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* 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
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* set Mode Clock Source = PCLK is generated from REFCLK
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*/
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usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO_ADDR, 0x0,
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usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO, 0x0,
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(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
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@ -721,19 +720,19 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
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CFG_PM_RXDLOZ_WAIT_MASK;
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data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
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usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1_ADDR, data, mask);
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usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask);
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/*
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* 9. Enable idle sync
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*/
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data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
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usb3_reg_set(reg_base, COMPHY_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
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usb3_reg_set(reg_base, COMPHY_UNIT_CTRL, data, REG_16_BIT_MASK);
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/*
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* 10. Enable the output of 500M clock
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*/
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data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
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usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
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usb3_reg_set(reg_base, COMPHY_MISC_REG0, data, REG_16_BIT_MASK);
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/*
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* 11. Set 20-bit data width
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@ -777,14 +776,13 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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* 16. Release SW reset
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*/
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data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
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usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0_ADDR, data,
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REG_16_BIT_MASK);
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usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0, data, REG_16_BIT_MASK);
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/* Wait for > 55 us to allow PCLK be enabled */
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udelay(PLL_SET_DELAY_US);
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if (comphy_index == COMPHY_LANE2) {
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data = COMPHY_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
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data = COMPHY_LANE_STATUS1 + USB3PHY_LANE2_REG_BASE_OFFSET;
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mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
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data);
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@ -121,36 +121,36 @@ enum {
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#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
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RSVD_PH03FH_6_0_OFF)
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#define COMPHY_UNIT_CTRL_ADDR 0x48
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#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL_ADDR * PHY_SHFT(unit))
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#define COMPHY_UNIT_CTRL 0x48
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#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL * PHY_SHFT(unit))
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#define IDLE_SYNC_EN BIT(12)
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#define UNIT_CTRL_DEFAULT_VALUE 0x60
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#define COMPHY_MISC_REG0_ADDR 0x4F
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#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
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#define COMPHY_MISC_REG0 0x4F
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#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0 * PHY_SHFT(unit))
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#define CLK100M_125M_EN BIT(4)
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#define TXDCLK_2X_SEL BIT(6)
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#define CLK500M_EN BIT(7)
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#define PHY_REF_CLK_SEL BIT(10)
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#define MISC_REG0_DEFAULT_VALUE 0xA00D
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#define COMPHY_MISC_REG1_ADDR 0x73
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#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
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#define COMPHY_MISC_REG1 0x73
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#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1 * PHY_SHFT(unit))
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#define SEL_BITS_PCIE_FORCE BIT(15)
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#define COMPHY_GEN2_SETTINGS_3 0x112
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#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
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#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
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#define COMPHY_LANE_CFG0_ADDR 0x180
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#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0_ADDR * PHY_SHFT(unit))
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#define COMPHY_LANE_CFG0 0x180
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#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit))
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#define PRD_TXDEEMPH0_MASK BIT(0)
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#define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
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#define PRD_TXSWING_MASK BIT(4)
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#define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
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#define COMPHY_LANE_CFG1_ADDR 0x181
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#define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1_ADDR * PHY_SHFT(unit))
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#define COMPHY_LANE_CFG1 0x181
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#define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1 * PHY_SHFT(unit))
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#define PRD_TXDEEMPH1_MASK BIT(15)
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#define USE_MAX_PLL_RATE_EN BIT(9)
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#define TX_DET_RX_MODE BIT(6)
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@ -158,18 +158,16 @@ enum {
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#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
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#define TX_ELEC_IDLE_MODE_EN BIT(0)
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#define COMPHY_LANE_STATUS1_ADDR 0x183
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#define LANE_STATUS1_ADDR(unit) (COMPHY_LANE_STATUS1_ADDR * \
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PHY_SHFT(unit))
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#define COMPHY_LANE_STATUS1 0x183
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#define LANE_STATUS1_ADDR(unit) (COMPHY_LANE_STATUS1 * PHY_SHFT(unit))
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#define TXDCLK_PCLK_EN BIT(0)
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#define COMPHY_LANE_CFG4_ADDR 0x188
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#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4_ADDR * PHY_SHFT(unit))
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#define COMPHY_LANE_CFG4 0x188
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#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit))
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#define SPREAD_SPECTRUM_CLK_EN BIT(7)
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#define COMPHY_GLOB_PHY_CTRL0_ADDR 0x1C1
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#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0_ADDR * \
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PHY_SHFT(unit))
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#define COMPHY_GLOB_PHY_CTRL0 0x1C1
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#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0 * PHY_SHFT(unit))
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#define SOFT_RESET BIT(0)
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#define MODE_CORE_CLK_FREQ_SEL BIT(9)
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#define MODE_PIPE_WIDTH_32 BIT(3)
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@ -178,13 +176,12 @@ enum {
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#define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET)
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#define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET)
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#define COMPHY_TEST_MODE_CTRL_ADDR 0x1C2
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#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL_ADDR * \
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PHY_SHFT(unit))
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#define COMPHY_TEST_MODE_CTRL 0x1C2
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#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit))
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#define MODE_MARGIN_OVERRIDE BIT(2)
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#define COMPHY_GLOB_CLK_SRC_LO_ADDR 0x1C3
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#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_GLOB_CLK_SRC_LO_ADDR * \
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#define COMPHY_GLOB_CLK_SRC_LO 0x1C3
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#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_GLOB_CLK_SRC_LO * \
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PHY_SHFT(unit))
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#define MODE_CLK_SRC BIT(0)
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#define BUNDLE_PERIOD_SEL BIT(1)
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@ -193,9 +190,8 @@ enum {
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#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
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#define CFG_SEL_20B BIT(15)
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#define COMPHY_PWR_MGM_TIM1_ADDR 0x1D0
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#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1_ADDR * \
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PHY_SHFT(unit))
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#define COMPHY_PWR_MGM_TIM1 0x1D0
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#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1 * PHY_SHFT(unit))
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#define CFG_PM_OSCCLK_WAIT_OFF 12
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#define CFG_PM_OSCCLK_WAIT_LEN 4
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#define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \
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