From b86e691eb36011ec3fde57f6496dd7f4e31353c1 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Thu, 25 May 2017 11:04:33 -0700 Subject: [PATCH] Tegra186: memctrl_v2: Set MC clients ordering as per client needs Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO) based on the latest info received from HW team as a part of BW issues debug. SMMU Client config register are obsolete from T186. Clean up the unnecessary register definitions and programming of these registers. Cleanup unnecessary macros as well. Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2 Signed-off-by: Krishna Reddy --- .../tegra/common/drivers/memctrl/memctrl_v2.c | 203 ++++++++++-------- .../nvidia/tegra/include/drivers/memctrl_v2.h | 169 ++++++--------- 2 files changed, 174 insertions(+), 198 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index 55b915223..de431b75b 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -87,6 +87,9 @@ static void tegra_memctrl_reconfig_mss_clients(void) * strongly ordered MSS clients. ROC needs to be single point * of control on overriding the memory type. So, remove TSA's * memtype override. + * + * MC clients with default SO_DEV override still enabled at TSA: + * AONW, BPMPW, SCEW, APEW */ #if ENABLE_AFI_DEVICE mc_set_tsa_passthrough(AFIW); @@ -106,63 +109,121 @@ static void tegra_memctrl_reconfig_mss_clients(void) mc_set_tsa_passthrough(AONDMAW); mc_set_tsa_passthrough(SCEDMAW); - /* - * Change COH_PATH_OVERRIDE_SO_DEV from NO_OVERRIDE -> FORCE_COHERENT - * for boot and strongly ordered MSS clients. This steers all sodev - * transactions to ROC. + /* Parker has no IO Coherency support and need the following: + * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB. + * ISO clients(DISP, VI, EQOS) should never snoop caches and + * don't need ROC/PCFIFO ordering. + * ISO clients(EQOS) that need ordering should use PCFIFO ordering + * and bypass ROC ordering by using FORCE_NON_COHERENT path. + * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence + * over SMMU attributes. + * Force all Normal memory transactions from ISO and non-ISO to be + * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). + * Force the SO_DEV transactions from ordered ISO clients(EQOS) to + * non-coherent path and enable MC PCFIFO interlock for ordering. + * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, + * XUSB, SATA) to coherent so that the transactions are + * ordered by ROC. + * PCFIFO ensure write ordering. + * Read after Write ordering is maintained/enforced by MC clients. + * Clients that need PCIe type write ordering must + * go through ROC ordering. + * Ordering enable for Read clients is not necessary. + * R5's and A9 would get necessary ordering from AXI and + * don't need ROC ordering enable: + * - MMIO ordering is through dev mapping and MMIO + * accesses bypass SMMU. + * - Normal memory is accessed through SMMU and ordering is + * ensured by client and AXI. + * - Ack point for Normal memory is WCAM in MC. + * - MMIO's can be early acked and AXI ensures dev memory ordering, + * Client ensures read/write direction change ordering. + * - See Bug 200312466 for more details. * - * Change AXID_OVERRIDE/AXID_OVERRIDE_SO_DEV only for some clients - * whose AXI IDs we know and trust. + * CGID_TAG_ADR is only present from T186 A02. As this code is common + * between A01 and A02, tegra_memctrl_set_overrides() programs + * CGID_TAG_ADR for the necessary clients on A02. */ - -#if ENABLE_AFI_DEVICE - /* Match AFIW */ - mc_set_forced_coherent_so_dev_cfg(AFIR); -#endif - + mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + /* See bug 200131110 comment #35*/ + mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + /* See bug 200131110 comment #35*/ + mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + /* See bug 200131110 comment #35 */ + mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); /* * See bug 200131110 comment #35 - there are no normal requests * and AWID for SO/DEV requests is hardcoded in RTL for a * particular PCIE controller */ -#if ENABLE_AFI_DEVICE - mc_set_forced_coherent_so_dev_cfg(AFIW); -#endif - mc_set_forced_coherent_cfg(HDAR); - mc_set_forced_coherent_cfg(HDAW); - mc_set_forced_coherent_cfg(SATAR); - mc_set_forced_coherent_cfg(SATAW); - mc_set_forced_coherent_cfg(XUSB_HOSTR); - mc_set_forced_coherent_cfg(XUSB_HOSTW); - mc_set_forced_coherent_cfg(XUSB_DEVR); - mc_set_forced_coherent_cfg(XUSB_DEVW); - mc_set_forced_coherent_cfg(SDMMCRAB); - mc_set_forced_coherent_cfg(SDMMCWAB); - - /* Match APEDMAW */ - mc_set_forced_coherent_axid_so_dev_cfg(APEDMAR); - - /* - * See bug 200131110 comment #35 - AWID for normal requests - * is 0x80 and AWID for SO/DEV requests is 0x01 - */ - mc_set_forced_coherent_axid_so_dev_cfg(APEDMAW); - mc_set_forced_coherent_cfg(SESRD); - mc_set_forced_coherent_cfg(SESWR); - mc_set_forced_coherent_cfg(ETRR); - mc_set_forced_coherent_cfg(ETRW); - mc_set_forced_coherent_cfg(AXISR); - mc_set_forced_coherent_cfg(AXISW); - mc_set_forced_coherent_cfg(EQOSR); - mc_set_forced_coherent_cfg(EQOSW); - mc_set_forced_coherent_cfg(UFSHCR); - mc_set_forced_coherent_cfg(UFSHCW); - mc_set_forced_coherent_cfg(BPMPDMAR); - mc_set_forced_coherent_cfg(BPMPDMAW); - mc_set_forced_coherent_cfg(AONDMAR); - mc_set_forced_coherent_cfg(AONDMAW); - mc_set_forced_coherent_cfg(SCEDMAR); - mc_set_forced_coherent_cfg(SCEDMAW); + mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); /* * At this point, ordering can occur at ROC. So, remove PCFIFO's @@ -192,56 +253,18 @@ static void tegra_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & - mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW) & mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); + /* EQOSW is the only client that has PCFIFO order enabled. */ + val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); - /* - * At this point, ordering can occur at ROC. SMMU need not - * reorder any requests. - * - * Change SMMU_*_ORDERED_CLIENT from ORDERED -> UNORDERED - * for boot and strongly ordered MSS clients - */ - val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL & -#if ENABLE_AFI_DEVICE - mc_set_smmu_unordered_boot_so_mss(1, AFIW) & -#endif - mc_set_smmu_unordered_boot_so_mss(1, HDAW) & - mc_set_smmu_unordered_boot_so_mss(1, SATAW); - tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val); - - val = MC_SMMU_CLIENT_CONFIG2_RESET_VAL & - mc_set_smmu_unordered_boot_so_mss(2, XUSB_HOSTW) & - mc_set_smmu_unordered_boot_so_mss(2, XUSB_DEVW); - tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG2, val); - - val = MC_SMMU_CLIENT_CONFIG3_RESET_VAL & - mc_set_smmu_unordered_boot_so_mss(3, SDMMCWAB); - tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG3, val); - - val = MC_SMMU_CLIENT_CONFIG4_RESET_VAL & - mc_set_smmu_unordered_boot_so_mss(4, SESWR) & - mc_set_smmu_unordered_boot_so_mss(4, ETRW) & - mc_set_smmu_unordered_boot_so_mss(4, AXISW) & - mc_set_smmu_unordered_boot_so_mss(4, EQOSW) & - mc_set_smmu_unordered_boot_so_mss(4, UFSHCW) & - mc_set_smmu_unordered_boot_so_mss(4, BPMPDMAW) & - mc_set_smmu_unordered_boot_so_mss(4, AONDMAW) & - mc_set_smmu_unordered_boot_so_mss(4, SCEDMAW); - tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG4, val); - - val = MC_SMMU_CLIENT_CONFIG5_RESET_VAL & - mc_set_smmu_unordered_boot_so_mss(5, APEDMAW); - tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG5, val); - /* * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS * clients to allow memory traffic from all clients to start passing diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index 957ff54c1..ffe5269a8 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -100,6 +100,19 @@ ******************************************************************************/ #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t)) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0UL << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1UL << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2UL << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3UL << 4) + +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0UL << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1UL << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2UL << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3UL << 8) + +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0UL << 12) +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1UL << 12) + /******************************************************************************* * Memory Controller transaction override config registers ******************************************************************************/ @@ -312,98 +325,51 @@ typedef struct tegra_mc_settings { /******************************************************************************* * Memory Controller's PCFIFO client configuration registers ******************************************************************************/ -#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 -#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000 -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29) -#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29) +#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4UL +#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000UL +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0UL << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1UL << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0UL << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1UL << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0UL << 29) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1UL << 29) -#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 -#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000 -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13) -#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13) +#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8UL +#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000UL +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0UL << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1UL << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0UL << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1UL << 13) -#define MC_PCFIFO_CLIENT_CONFIG3 0xddc -#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0 -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7) -#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7) +#define MC_PCFIFO_CLIENT_CONFIG3 0xddcUL +#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0UL +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0UL << 7) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1UL << 7) -#define MC_PCFIFO_CLIENT_CONFIG4 0xde0 -#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0 -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30) +#define MC_PCFIFO_CLIENT_CONFIG4 0xde0UL +#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0UL +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0UL << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1UL << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0UL << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1UL << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0UL << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1UL << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0UL << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1UL << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1UL << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0UL << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1UL << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0UL << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1UL << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0UL << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1UL << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0UL << 30) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1UL << 30) -#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 -#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0 -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0) -#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0) - -/******************************************************************************* - * Memory Controller's SMMU client configuration registers - ******************************************************************************/ -#define MC_SMMU_CLIENT_CONFIG1 0x44 -#define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000 -#define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17) -#define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17) -#define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21) -#define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21) -#define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29) -#define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29) - -#define MC_SMMU_CLIENT_CONFIG2 0x48 -#define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000 -#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11) -#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11) -#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13) -#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13) - -#define MC_SMMU_CLIENT_CONFIG3 0x4c -#define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0 -#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7) -#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7) - -#define MC_SMMU_CLIENT_CONFIG4 0xb9c -#define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0 -#define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1) -#define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1) -#define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5) -#define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5) -#define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13) -#define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13) -#define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15) -#define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15) -#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17) -#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17) -#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22) -#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22) -#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26) -#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26) -#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30) -#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30) - -#define MC_SMMU_CLIENT_CONFIG5 0xbac -#define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0 -#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0) -#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0) +#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4UL +#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0UL +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0UL << 0) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1UL << 0) #ifndef __ASSEMBLY__ @@ -433,9 +399,8 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) -#define mc_set_smmu_unordered_boot_so_mss(id, client) \ - (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ - MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) +#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \ + MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED #define mc_set_tsa_passthrough(client) \ { \ @@ -445,25 +410,13 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ } -#define mc_set_forced_coherent_cfg(client) \ +#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \ { \ tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ - MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \ - } - -#define mc_set_forced_coherent_so_dev_cfg(client) \ - { \ - tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ - MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ - MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ - } - -#define mc_set_forced_coherent_axid_so_dev_cfg(client) \ - { \ - tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ - MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ - MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \ - MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ + MC_TXN_OVERRIDE_##normal_axi_id | \ + MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \ + MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \ + MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ } /*******************************************************************************