Tegra186: reset CPU power state info while onlining
This patch resets the CPU power state info when we online any CPU. The NS world software would re-init the CPU power state after the CPU gets online anyways. This allows us to maintain proper CPU/cluster power states in the MCE firmware at all times. Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -242,27 +242,33 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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int state_id = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
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int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
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int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0];
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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/*
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* Reset power state info for CPUs when onlining, we set deepest power
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* when offlining a core but that may not be requested by non-secure
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* sw which controls idle states. It will re-init this info from
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* non-secure software when the core come online.
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* Reset power state info for CPUs when onlining, we set
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* deepest power when offlining a core but that may not be
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* requested by non-secure sw which controls idle states. It
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* will re-init this info from non-secure software when the
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* core come online.
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*/
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1,
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0, 0);
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if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
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TEGRA_ARI_CLUSTER_CC1, 0, 0);
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}
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/*
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* Check if we are exiting from deep sleep and restore SE
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* context if we are.
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*/
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if (state_id == PSTATE_ID_SOC_POWERDN) {
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
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se_regs[0]);
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mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
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