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Tegra186: reset CPU power state info while onlining 

This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
online anyways. This allows us to maintain proper CPU/cluster power
states in the MCE firmware at all times.

Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-04-29 11:25:46 -07:00
parent 2079ddd62c
commit b8de847359
1 changed files with 17 additions and 11 deletions
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22
plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
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@ -242,27 +242,33 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{ {
int state_id = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0];
cpu_context_t *ctx = cm_get_context(NON_SECURE); cpu_context_t *ctx = cm_get_context(NON_SECURE);
gp_regs_t *gp_regs = get_gpregs_ctx(ctx); gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
/* /*
* Reset power state info for CPUs when onlining, we set deepest power * Reset power state info for CPUs when onlining, we set
* when offlining a core but that may not be requested by non-secure * deepest power when offlining a core but that may not be
* sw which controls idle states. It will re-init this info from * requested by non-secure sw which controls idle states. It
* non-secure software when the core come online. * will re-init this info from non-secure software when the
* core come online.
*/ */
if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1, mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
0, 0); TEGRA_ARI_CLUSTER_CC1, 0, 0);
}
/* /*
* Check if we are exiting from deep sleep and restore SE * Check if we are exiting from deep sleep and restore SE
* context if we are. * context if we are.
*/ */
if (state_id == PSTATE_ID_SOC_POWERDN) { if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
se_regs[0]); se_regs[0]);
mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,