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marvell: uart: a3720: Fix macro name for 6th bit of Status Register 

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
This commit is contained in:
Pali Rohár 2021-01-18 12:52:55 +01:00
parent 74867756ef
commit b8e637f49e
2 changed files with 7 additions and 7 deletions
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12
drivers/marvell/uart/a3700_console.S
View File

@ -60,14 +60,14 @@ func console_a3700_core_init
str w3, [x0, #UART_POSSR_REG]
/*
* Wait for the TX FIFO to be empty. If wait for 20ms, the TX FIFO is
* Wait for the TX (THR and TSR) to be empty. If wait for 20ms, the TX FIFO is
* still not empty, TX FIFO will reset by all means.
*/
mov w1, #20 /* max time out 20ms */
2:
/* Check whether TX FIFO is empty */
/* Check whether TX (THR and TSR) is empty */
ldr w3, [x0, #UART_STATUS_REG]
and w3, w3, #UARTLSR_TXFIFOEMPTY
and w3, w3, #UARTLSR_TXEMPTY
cmp w3, #0
b.ne 4f
@ -241,10 +241,10 @@ endfunc console_a3700_getc
* ---------------------------------------------
*/
func console_a3700_core_flush
/* Wait for the TX FIFO to be empty */
/* Wait for the TX (THR and TSR) to be empty */
1: ldr w1, [x0, #UART_STATUS_REG]
and w1, w1, #UARTLSR_TXFIFOEMPTY
cmp w1, #UARTLSR_TXFIFOEMPTY
and w1, w1, #UARTLSR_TXEMPTY
cmp w1, #UARTLSR_TXEMPTY
b.ne 1b
ret
endfunc console_a3700_core_flush

2
include/drivers/marvell/uart/a3700_console.h
View File

@ -48,12 +48,12 @@
/* Line Status Register bits */
#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
#define UARTLSR_TXEMPTY (1 << 6) /* Tx Empty */
#define UARTLSR_RXRDY (1 << 4) /* Rx Ready */
/* UART Control Register bits */
#define UART_CTRL_RXFIFO_RESET (1 << 14)
#define UART_CTRL_TXFIFO_RESET (1 << 15)
#define UARTLSR_TXFIFOEMPTY (1 << 6)
#ifndef __ASSEMBLER__