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fix(stm32mp1_clk): fix MCU/AXI parent clock 

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock  PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is derived
from clock  PLL2_P, not PLL2.

This change also renames MCU clock and AXI clock resources to
prevent confusion.

Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit is contained in:
Etienne Carriere 2019-12-19 10:03:23 +01:00 committed by Yann Gautier
parent ba57711c38
commit b8fe48b6f2
1 changed files with 6 additions and 6 deletions
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12
drivers/st/clk/stm32mp1_clk.c
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@ -467,12 +467,12 @@ static const uint8_t fmc_parents[] = {
_ACLK, _PLL3_R, _PLL4_P, _CK_PER
};
static const uint8_t ass_parents[] = {
_HSI, _HSE, _PLL2
static const uint8_t axiss_parents[] = {
_HSI, _HSE, _PLL2_P
};
static const uint8_t mss_parents[] = {
_HSI, _HSE, _CSI, _PLL3
static const uint8_t mcuss_parents[] = {
_HSI, _HSE, _CSI, _PLL3_P
};
static const uint8_t usbphy_parents[] = {
@ -514,8 +514,8 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
_CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
_CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
_CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
_CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
_CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
_CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents),
_CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents),
_CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
_CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
};