zynqmp: FSBL->ATF handover
Parse the parameter structure the FSBL populates, to populate the bl32 and bl33 image structures. Cc: Sarat Chand Savitala <saratcha@xilinx.com> Cc: petalinux-dev@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> [ SB - pass pointers to structs instead of structs - handle execution state parameter - populate bl32 SPSR - add documentation - query bootmode and consider missing handoff parameters an error when not in JTAG boot mode ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This commit is contained in:
Michal Simek
Soren Brinkmann
parent
2cb5bac984
commit
b96f77c65b
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@ -26,6 +26,13 @@ make ERROR_DEPRECATED=1 RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zyn
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* `ZYNQMP_BL32_MEM_BASE`: Specifies the base address of the bl32 binary.
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* `ZYNQMP_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
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# FSBL->ATF Parameter Passing
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The FSBL populates a data structure with image information for the ATF. The ATF
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uses that data to hand off to the loaded images. The address of the handoff data
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structure is passed in the ```PMU_GLOBAL.GLOBAL_GEN_STORAGE6``` register. The
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register is free to be used by other software once the ATF is bringing up
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further firmware images.
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# Power Domain Tree
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The following power domain tree represents the power domain model used by the
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ATF for ZynqMP:
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@ -113,25 +113,25 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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* present.
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*/
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/* Populate entry point information for BL32 and BL33 */
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/* Populate common information for BL32 and BL33 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
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/* use build time defaults in JTAG boot mode */
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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} else {
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/* use parameters from FSBL */
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fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info);
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}
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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}
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@ -0,0 +1,288 @@
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/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include "zynqmp_def.h"
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/*
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* ATFHandoffParams
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* Parameter bitfield encoding
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* -----------------------------------------------------------------------------
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* Exec State 0 0 -> Aarch64, 1-> Aarch32
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* endianess 1 0 -> LE, 1 -> BE
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* secure (TZ) 2 0 -> Non secure, 1 -> secure
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* EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3
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* CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3
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*/
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#define FSBL_FLAGS_ESTATE_SHIFT 0
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#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT)
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#define FSBL_FLAGS_ESTATE_A64 0
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#define FSBL_FLAGS_ESTATE_A32 1
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#define FSBL_FLAGS_ENDIAN_SHIFT 1
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#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT)
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#define FSBL_FLAGS_ENDIAN_LE 0
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#define FSBL_FLAGS_ENDIAN_BE 1
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#define FSBL_FLAGS_TZ_SHIFT 2
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#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT)
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#define FSBL_FLAGS_NON_SECURE 0
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#define FSBL_FLAGS_SECURE 1
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#define FSBL_FLAGS_EL_SHIFT 3
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#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT)
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#define FSBL_FLAGS_EL0 0
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#define FSBL_FLAGS_EL1 1
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#define FSBL_FLAGS_EL2 2
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#define FSBL_FLAGS_EL3 3
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#define FSBL_FLAGS_CPU_SHIFT 5
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#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT)
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#define FSBL_FLAGS_A53_0 0
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#define FSBL_FLAGS_A53_1 1
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#define FSBL_FLAGS_A53_2 2
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#define FSBL_FLAGS_A53_3 3
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#define FSBL_MAX_PARTITIONS 8
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/* Structure corresponding to each partition entry */
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struct xfsbl_partition {
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uint64_t entry_point;
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uint64_t flags;
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};
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/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */
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struct xfsbl_atf_handoff_params {
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uint8_t magic[4];
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uint32_t num_entries;
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struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
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};
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/**
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* @partition: Pointer to partition struct
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*
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* Get the target CPU for @partition.
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*
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* Return: FSBL_FLAGS_A53_0, FSBL_FLAGS_A53_1, FSBL_FLAGS_A53_2 or FSBL_FLAGS_A53_3
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*/
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static int get_fsbl_cpu(const struct xfsbl_partition *partition)
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{
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uint64_t flags = partition->flags & FSBL_FLAGS_CPU_MASK;
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return flags >> FSBL_FLAGS_CPU_SHIFT;
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}
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/**
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* @partition: Pointer to partition struct
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*
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* Get the target exception level for @partition.
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*
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* Return: FSBL_FLAGS_EL0, FSBL_FLAGS_EL1, FSBL_FLAGS_EL2 or FSBL_FLAGS_EL3
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*/
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static int get_fsbl_el(const struct xfsbl_partition *partition)
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{
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uint64_t flags = partition->flags & FSBL_FLAGS_EL_MASK;
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return flags >> FSBL_FLAGS_EL_SHIFT;;
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}
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/**
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* @partition: Pointer to partition struct
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*
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* Get the target security state for @partition.
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*
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* Return: FSBL_FLAGS_NON_SECURE or FSBL_FLAGS_SECURE
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*/
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static int get_fsbl_ss(const struct xfsbl_partition *partition)
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{
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uint64_t flags = partition->flags & FSBL_FLAGS_TZ_MASK;
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return flags >> FSBL_FLAGS_TZ_SHIFT;
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}
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/**
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* @partition: Pointer to partition struct
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*
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* Get the target endianess for @partition.
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*
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* Return: SPSR_E_LITTLE or SPSR_E_BIG
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*/
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static int get_fsbl_endian(const struct xfsbl_partition *partition)
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{
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uint64_t flags = partition->flags & FSBL_FLAGS_ENDIAN_MASK;
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flags >>= FSBL_FLAGS_ENDIAN_SHIFT;
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if (flags == FSBL_FLAGS_ENDIAN_BE)
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return SPSR_E_BIG;
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else
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return SPSR_E_LITTLE;
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}
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/**
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* @partition: Pointer to partition struct
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*
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* Get the target execution state for @partition.
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*
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* Return: FSBL_FLAGS_ESTATE_A32 or FSBL_FLAGS_ESTATE_A64
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*/
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static int get_fsbl_estate(const struct xfsbl_partition *partition)
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{
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uint64_t flags = partition->flags & FSBL_FLAGS_ESTATE_MASK;
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return flags >> FSBL_FLAGS_ESTATE_SHIFT;
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}
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/**
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* Populates the bl32 and bl33 image info structures
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* @bl32: BL32 image info structure
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* @bl33: BL33 image info structure
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*
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* Process the handoff paramters from the FSBL and populate the BL32 and BL33
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* image info structures accordingly.
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*/
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void fsbl_atf_handover(entry_point_info_t *bl32, entry_point_info_t *bl33)
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{
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uint64_t atf_handoff_addr;
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const struct xfsbl_atf_handoff_params *ATFHandoffParams;
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atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
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assert((atf_handoff_addr < BL31_BASE) ||
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(atf_handoff_addr > (uint64_t)&__BL31_END__));
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if (!atf_handoff_addr) {
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ERROR("BL31: No ATF handoff structure passed\n");
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panic();
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}
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ATFHandoffParams = (struct xfsbl_atf_handoff_params *)atf_handoff_addr;
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if ((ATFHandoffParams->magic[0] != 'X') ||
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(ATFHandoffParams->magic[1] != 'L') ||
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(ATFHandoffParams->magic[2] != 'N') ||
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(ATFHandoffParams->magic[3] != 'X')) {
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ERROR("BL31: invalid ATF handoff structure at %lx\n",
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atf_handoff_addr);
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panic();
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}
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VERBOSE("BL31: ATF handoff params at:0x%lx, entries:%u\n",
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atf_handoff_addr, ATFHandoffParams->num_entries);
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if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) {
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ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n",
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ATFHandoffParams->num_entries, FSBL_MAX_PARTITIONS);
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panic();
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}
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/*
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* we loop over all passed entries but only populate two image structs
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* (bl32, bl33). I.e. the last applicable images in the handoff
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* structure will be used for the hand off
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*/
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for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) {
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entry_point_info_t *image;
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int target_estate, target_secure;
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int target_cpu, target_endianess, target_el;
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VERBOSE("BL31: %zd: entry:0x%lx, flags:0x%lx\n", i,
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ATFHandoffParams->partition[i].entry_point,
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ATFHandoffParams->partition[i].flags);
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target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]);
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if (target_cpu != FSBL_FLAGS_A53_0) {
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WARN("BL31: invalid target CPU (%i)\n", target_cpu);
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continue;
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}
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target_el = get_fsbl_el(&ATFHandoffParams->partition[i]);
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if ((target_el == FSBL_FLAGS_EL3) ||
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(target_el == FSBL_FLAGS_EL0)) {
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WARN("BL31: invalid exception level (%i)\n", target_el);
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continue;
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}
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target_secure = get_fsbl_ss(&ATFHandoffParams->partition[i]);
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if (target_secure == FSBL_FLAGS_SECURE &&
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target_el == FSBL_FLAGS_EL2) {
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WARN("BL31: invalid security state (%i) for exception level (%i)\n",
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target_secure, target_el);
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continue;
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}
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target_estate = get_fsbl_estate(&ATFHandoffParams->partition[i]);
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target_endianess = get_fsbl_endian(&ATFHandoffParams->partition[i]);
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if (target_secure == FSBL_FLAGS_SECURE) {
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image = bl32;
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if (target_estate == FSBL_FLAGS_ESTATE_A32)
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bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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target_endianess,
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DISABLE_ALL_EXCEPTIONS);
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else
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bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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} else {
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image = bl33;
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if (target_estate == FSBL_FLAGS_ESTATE_A32) {
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if (target_el == FSBL_FLAGS_EL2)
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target_el = MODE32_hyp;
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else
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target_el = MODE32_sys;
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bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM,
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target_endianess,
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DISABLE_ALL_EXCEPTIONS);
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} else {
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if (target_el == FSBL_FLAGS_EL2)
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target_el = MODE_EL2;
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else
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target_el = MODE_EL1;
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bl33->spsr = SPSR_64(target_el, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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}
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VERBOSE("Setting up %s entry point to:%lx, el:%x\n",
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target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33",
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ATFHandoffParams->partition[i].entry_point,
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target_el);
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image->pc = ATFHandoffParams->partition[i].entry_point;
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if (target_endianess == SPSR_E_BIG)
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EP_SET_EE(image->h.attr, EP_EE_BIG);
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else
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EP_SET_EE(image->h.attr, EP_EE_LITTLE);
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}
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}
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@ -82,6 +82,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
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plat/xilinx/zynqmp/plat_psci.c \
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plat/xilinx/zynqmp/plat_zynqmp.c \
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plat/xilinx/zynqmp/plat_startup.c \
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plat/xilinx/zynqmp/plat_topology.c \
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plat/xilinx/zynqmp/sip_svc_setup.c \
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plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
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@ -98,6 +98,7 @@
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/* PMU registers and bitfields */
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#define PMU_GLOBAL_BASE 0xFFD80000
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#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
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#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
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#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
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#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
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#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
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@ -40,4 +40,8 @@ unsigned int zynqmp_get_uart_clk(void);
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int zynqmp_is_pmu_up(void);
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unsigned int zynqmp_get_bootmode(void);
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/* For FSBL handover */
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void fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info,
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entry_point_info_t *bl33_image_ep_info);
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#endif /* __ZYNQMP_PRIVATE_H__ */
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