From 75a1ada95efa78e4133bdd947c64944005a8e5c2 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Mon, 4 Mar 2019 16:56:26 +0000 Subject: [PATCH 1/2] Cortex-A15: Implement workaround for errata 816470 Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent --- docs/cpu-specific-build-macros.rst | 5 +++++ lib/cpus/aarch32/cortex_a15.S | 24 +++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 ++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 95538d02b..a9ed9c1b4 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -71,6 +71,11 @@ for it to specify which errata workarounds should be enabled or not. The value of the build flags is 0 by default, that is, disabled. A value of 1 will enable it. +For Cortex-A15, the following errata build flags are defined : + +- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 + CPU. This needs to be enabled only for revision >= r3p0 of the CPU. + For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index b6c61ab7f..8c3bbf41e 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,6 +29,13 @@ func cortex_a15_disable_smp bic r0, #CORTEX_A15_ACTLR_SMP_BIT stcopr r0, ACTLR isb +#if ERRATA_A15_816470 + /* + * Invalidate any TLB address + */ + mov r0, #0 + stcopr r0, TLBIMVA +#endif dsb sy bx lr endfunc cortex_a15_disable_smp @@ -41,6 +48,20 @@ func cortex_a15_enable_smp bx lr endfunc cortex_a15_enable_smp + /* ---------------------------------------------------- + * Errata Workaround for Cortex A15 Errata #816470. + * This applies only to revision >= r3p0 of Cortex A15. + * ---------------------------------------------------- + */ +func check_errata_816470 + /* + * Even though this is only needed for revision >= r3p0, it is always + * applied because of the low cost of the workaround. + */ + mov r0, #ERRATA_APPLIES + bx lr +endfunc check_errata_816470 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -64,6 +85,7 @@ func cortex_a15_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A15_816470, cortex_a15, 816470 report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715 pop {r12, lr} diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4985dd062..a82db106c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -53,6 +53,10 @@ endif # These should be enabled by the platform if the erratum workaround needs to be # applied. +# Flag to apply erratum 816470 workaround during power down. This erratum +# applies only to revision >= r3p0 of the Cortex A15 cpu. +ERRATA_A15_816470 ?=0 + # Flag to apply erratum 819472 workaround during reset. This erratum applies # only to revision <= r0p1 of the Cortex A53 cpu. ERRATA_A53_819472 ?=0 @@ -196,6 +200,10 @@ ERRATA_N1_1043202 ?=1 # higher DSU power consumption on idle. ERRATA_DSU_936184 ?=0 +# Process ERRATA_A15_816470 flag +$(eval $(call assert_boolean,ERRATA_A15_816470)) +$(eval $(call add_define,ERRATA_A15_816470)) + # Process ERRATA_A53_819472 flag $(eval $(call assert_boolean,ERRATA_A53_819472)) $(eval $(call add_define,ERRATA_A53_819472)) From 5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23 Mon Sep 17 00:00:00 2001 From: Ambroise Vincent Date: Tue, 5 Mar 2019 09:54:21 +0000 Subject: [PATCH 2/2] Cortex-A15: Implement workaround for errata 827671 This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent --- docs/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch32/cortex_a15.h | 7 +++++ lib/cpus/aarch32/cortex_a15.S | 39 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 57 insertions(+) diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index a9ed9c1b4..8c951de00 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -76,6 +76,9 @@ For Cortex-A15, the following errata build flags are defined : - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. +- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 + CPU. This needs to be enabled only for revision >= r3p0 of the CPU. + For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 957afbdb4..9526a9cef 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -9,6 +9,13 @@ #include +/******************************************************************************* + * Auxiliary Control Register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4 + +#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0) + /******************************************************************************* * Cortex-A15 midr with version/revision set to 0 ******************************************************************************/ diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 8c3bbf41e..ab136adf4 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -62,6 +62,35 @@ func check_errata_816470 bx lr endfunc check_errata_816470 + /* ---------------------------------------------------- + * Errata Workaround for Cortex A15 Errata #827671. + * This applies only to revision >= r3p0 of Cortex A15. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * ---------------------------------------------------- + */ +func errata_a15_827671_wa + /* + * Compare r0 against revision r3p0 + */ + mov r2, lr + bl check_errata_827671 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr r0, CORTEX_A15_ACTLR2 + orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT + stcopr r0, CORTEX_A15_ACTLR2 + isb +1: + bx r2 +endfunc errata_a15_827671_wa + +func check_errata_827671 + mov r1, #0x30 + b cpu_rev_var_hs +endfunc check_errata_827671 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -86,6 +115,7 @@ func cortex_a15_errata_report * checking functions of each errata. */ report_errata ERRATA_A15_816470, cortex_a15, 816470 + report_errata ERRATA_A15_827671, cortex_a15, 827671 report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715 pop {r12, lr} @@ -94,6 +124,13 @@ endfunc cortex_a15_errata_report #endif func cortex_a15_reset_func + mov r5, lr + bl cpu_get_rev_var + +#if ERRATA_A15_827671 + bl errata_a15_827671_wa +#endif + #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 ldcopr r0, ACTLR orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT @@ -103,6 +140,8 @@ func cortex_a15_reset_func stcopr r0, MVBAR /* isb will be applied in the course of the reset func */ #endif + + mov lr, r5 b cortex_a15_enable_smp endfunc cortex_a15_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a82db106c..f178f1af2 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -57,6 +57,10 @@ endif # applies only to revision >= r3p0 of the Cortex A15 cpu. ERRATA_A15_816470 ?=0 +# Flag to apply erratum 827671 workaround during reset. This erratum applies +# only to revision >= r3p0 of the Cortex A15 cpu. +ERRATA_A15_827671 ?=0 + # Flag to apply erratum 819472 workaround during reset. This erratum applies # only to revision <= r0p1 of the Cortex A53 cpu. ERRATA_A53_819472 ?=0 @@ -204,6 +208,10 @@ ERRATA_DSU_936184 ?=0 $(eval $(call assert_boolean,ERRATA_A15_816470)) $(eval $(call add_define,ERRATA_A15_816470)) +# Process ERRATA_A15_827671 flag +$(eval $(call assert_boolean,ERRATA_A15_827671)) +$(eval $(call add_define,ERRATA_A15_827671)) + # Process ERRATA_A53_819472 flag $(eval $(call assert_boolean,ERRATA_A53_819472)) $(eval $(call add_define,ERRATA_A53_819472))