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fix(plat/xilinx/versal): resolve misra R15.6 

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: If1ccaa2f254ac85a329295de501e2b5558e8ff43
This commit is contained in:
Abhyuday Godhasara 2021-08-09 08:15:13 -07:00
parent 775bf1bbd3
commit b9fa2d9fc1
1 changed files with 18 additions and 10 deletions
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28
plat/xilinx/versal/plat_psci.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -26,8 +26,9 @@ static int versal_pwr_domain_on(u_register_t mpidr)
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
if (cpu_id == -1) if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL; return PSCI_E_INTERN_FAIL;
}
proc = pm_get_proc(cpu_id); proc = pm_get_proc(cpu_id);
@ -53,9 +54,10 @@ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
unsigned int cpu_id = plat_my_core_pos(); unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id); const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]); __func__, i, target_state->pwr_domain_state[i]);
}
plat_versal_gic_cpuif_disable(); plat_versal_gic_cpuif_disable();
@ -89,9 +91,10 @@ static void versal_pwr_domain_suspend_finish(
unsigned int cpu_id = plat_my_core_pos(); unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id); const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]); __func__, i, target_state->pwr_domain_state[i]);
}
/* Clear the APU power control register for this cpu */ /* Clear the APU power control register for this cpu */
pm_client_wakeup(proc); pm_client_wakeup(proc);
@ -126,8 +129,9 @@ static void __dead2 versal_system_off(void)
pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope(), SECURE_FLAG); pm_get_shutdown_scope(), SECURE_FLAG);
while (1) while (1) {
wfi(); wfi();
}
} }
/** /**
@ -140,8 +144,9 @@ static void __dead2 versal_system_reset(void)
pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope(), SECURE_FLAG); pm_get_shutdown_scope(), SECURE_FLAG);
while (1) while (1) {
wfi(); wfi();
}
} }
/** /**
@ -154,9 +159,10 @@ static void versal_pwr_domain_off(const psci_power_state_t *target_state)
unsigned int cpu_id = plat_my_core_pos(); unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id); const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]); __func__, i, target_state->pwr_domain_state[i]);
}
/* Prevent interrupts from spuriously waking up this cpu */ /* Prevent interrupts from spuriously waking up this cpu */
plat_versal_gic_cpuif_disable(); plat_versal_gic_cpuif_disable();
@ -192,14 +198,16 @@ static int versal_validate_power_state(unsigned int power_state,
assert(req_state); assert(req_state);
/* Sanity check the requested state */ /* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) if (pstate == PSTATE_TYPE_STANDBY) {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
else } else {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */ /* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state)) if (psci_get_pstate_id(power_state)) {
return PSCI_E_INVALID_PARAMS; return PSCI_E_INVALID_PARAMS;
}
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }