From a601afe1585e8d53afb7c1ea87d0ba7a5bb85bd3 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:23:50 -0500 Subject: [PATCH 01/10] Workaround for Neoverse N1 erratum 1073348 Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 5 ++++ include/lib/cpus/aarch64/neoverse_n1.h | 4 +++ lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 50 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 6b524c24c..55109dc7d 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -226,6 +226,11 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +For Neoverse N1, the following errata build flags are defined : + +- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b66aeb8a0..9048f4372 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -33,6 +33,10 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) + #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 8afc4a283..2d427b608 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -75,6 +75,33 @@ func neoverse_n1_disable_speculative_loads ret endfunc neoverse_n1_disable_speculative_loads +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1073348 + * This applies to revision r0p0 and r1p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1073348_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1073348 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 + msr NEOVERSE_N1_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1073348_wa + +func check_errata_1073348 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1073348 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -123,6 +150,11 @@ func neoverse_n1_reset_func bl errata_n1_1043202_wa #endif +#if ERRATA_N1_1073348 + mov x0, x18 + bl errata_n1_1073348_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -185,6 +217,7 @@ func neoverse_n1_errata_report * checking functions of each errata. */ report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 + report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index db4537528..0d00d0adc 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -238,6 +238,10 @@ ERRATA_A76_1286807 ?=0 # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 +# Flag to apply erratum 1073348 workaround during reset. This erratum applies +# only to revision r0p0 and r1p0 of the Neoverse N1 cpu. +ERRATA_N1_1073348 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -431,6 +435,10 @@ $(eval $(call add_define,ERRATA_A76_1286807)) $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) +# Process ERRATA_N1_1073348 flag +$(eval $(call assert_boolean,ERRATA_N1_1073348)) +$(eval $(call add_define,ERRATA_N1_1073348)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From e34606f2e400c192bac3abeb9b2053b2c91ccd7c Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:28:34 -0500 Subject: [PATCH 02/10] Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 46 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 55109dc7d..01ee41625 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -231,6 +231,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. +- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9048f4372..9042d7031 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -41,6 +41,8 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 2d427b608..31708a4e6 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -102,6 +102,33 @@ func check_errata_1073348 b cpu_rev_var_ls endfunc check_errata_1073348 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1130799 + * This applies to revision <=r2p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1130799_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_1130799 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 + msr NEOVERSE_N1_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1130799_wa + +func check_errata_1130799 + /* Applies to <=r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1130799 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -155,6 +182,11 @@ func neoverse_n1_reset_func bl errata_n1_1073348_wa #endif +#if ERRATA_N1_1130799 + mov x0, x18 + bl errata_n1_1130799_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -218,6 +250,7 @@ func neoverse_n1_errata_report */ report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 + report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0d00d0adc..676667b63 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -242,6 +242,10 @@ ERRATA_N1_1043202 ?=1 # only to revision r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1073348 ?=0 +# Flag to apply erratum 1130799 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Neoverse N1 cpu. +ERRATA_N1_1130799 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -439,6 +443,10 @@ $(eval $(call add_define,ERRATA_N1_1043202)) $(eval $(call assert_boolean,ERRATA_N1_1073348)) $(eval $(call add_define,ERRATA_N1_1073348)) +# Process ERRATA_N1_1130799 flag +$(eval $(call assert_boolean,ERRATA_N1_1130799)) +$(eval $(call add_define,ERRATA_N1_1130799)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 2017ab241c6634ecc184f09a39e77a06146403b0 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:32:40 -0500 Subject: [PATCH 03/10] Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 ++ include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ lib/cpus/aarch64/neoverse_n1.S | 34 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 47 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 01ee41625..fd99d8e90 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -234,6 +234,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9042d7031..7950cd220 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -39,7 +39,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 31708a4e6..a8ffa2546 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -129,6 +129,34 @@ func check_errata_1130799 b cpu_rev_var_ls endfunc check_errata_1130799 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1165347 + * This applies to revision <=r2p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1165347_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_1165347 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 + orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 + msr NEOVERSE_N1_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1165347_wa + +func check_errata_1165347 + /* Applies to <=r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1165347 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -187,6 +215,11 @@ func neoverse_n1_reset_func bl errata_n1_1130799_wa #endif +#if ERRATA_N1_1165347 + mov x0, x18 + bl errata_n1_1165347_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -251,6 +284,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 + report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 676667b63..faaf1203b 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -246,6 +246,10 @@ ERRATA_N1_1073348 ?=0 # only to revision <= r2p0 of the Neoverse N1 cpu. ERRATA_N1_1130799 ?=0 +# Flag to apply erratum 1165347 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Neoverse N1 cpu. +ERRATA_N1_1165347 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -447,6 +451,10 @@ $(eval $(call add_define,ERRATA_N1_1073348)) $(eval $(call assert_boolean,ERRATA_N1_1130799)) $(eval $(call add_define,ERRATA_N1_1130799)) +# Process ERRATA_N1_1165347 flag +$(eval $(call assert_boolean,ERRATA_N1_1165347)) +$(eval $(call add_define,ERRATA_N1_1165347)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From ef5fa7d47741d008f8786f971fc138e6331fb46d Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:35:37 -0500 Subject: [PATCH 04/10] Workaround for Neoverse N1 erratum 1207823 Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 1 + lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 45 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index fd99d8e90..ef24f2e39 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -237,6 +237,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 7950cd220..8925827e9 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -41,6 +41,7 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index a8ffa2546..c9bcea898 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -157,6 +157,33 @@ func check_errata_1165347 b cpu_rev_var_ls endfunc check_errata_1165347 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1207823 + * This applies to revision <=r2p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1207823_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_1207823 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 + msr NEOVERSE_N1_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1207823_wa + +func check_errata_1207823 + /* Applies to <=r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1207823 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -220,6 +247,11 @@ func neoverse_n1_reset_func bl errata_n1_1165347_wa #endif +#if ERRATA_N1_1207823 + mov x0, x18 + bl errata_n1_1207823_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -285,6 +317,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 + report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index faaf1203b..78efbeb3c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -250,6 +250,10 @@ ERRATA_N1_1130799 ?=0 # only to revision <= r2p0 of the Neoverse N1 cpu. ERRATA_N1_1165347 ?=0 +# Flag to apply erratum 1207823 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Neoverse N1 cpu. +ERRATA_N1_1207823 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -455,6 +459,10 @@ $(eval $(call add_define,ERRATA_N1_1130799)) $(eval $(call assert_boolean,ERRATA_N1_1165347)) $(eval $(call add_define,ERRATA_N1_1165347)) +# Process ERRATA_N1_1207823 flag +$(eval $(call assert_boolean,ERRATA_N1_1207823)) +$(eval $(call add_define,ERRATA_N1_1207823)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 9eceb020d79614cf41d64f6eae4086f3b5390203 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:38:53 -0500 Subject: [PATCH 05/10] Workaround for Neoverse N1 erratum 1220197 Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 2 ++ lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 46 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index ef24f2e39..ee8da1767 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -240,6 +240,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 8925827e9..952ae6ebe 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -30,6 +30,8 @@ ******************************************************************************/ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index c9bcea898..0e7b8e8cc 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -184,6 +184,33 @@ func check_errata_1207823 b cpu_rev_var_ls endfunc check_errata_1207823 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1220197 + * This applies to revision <=r2p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1220197_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_1220197 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUECTLR_EL1 + orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK + msr NEOVERSE_N1_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1220197_wa + +func check_errata_1220197 + /* Applies to <=r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1220197 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -252,6 +279,11 @@ func neoverse_n1_reset_func bl errata_n1_1207823_wa #endif +#if ERRATA_N1_1220197 + mov x0, x18 + bl errata_n1_1220197_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -318,6 +350,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 + report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 78efbeb3c..bb53dad0a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -254,6 +254,10 @@ ERRATA_N1_1165347 ?=0 # only to revision <= r2p0 of the Neoverse N1 cpu. ERRATA_N1_1207823 ?=0 +# Flag to apply erratum 1220197 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Neoverse N1 cpu. +ERRATA_N1_1220197 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -463,6 +467,10 @@ $(eval $(call add_define,ERRATA_N1_1165347)) $(eval $(call assert_boolean,ERRATA_N1_1207823)) $(eval $(call add_define,ERRATA_N1_1207823)) +# Process ERRATA_N1_1220197 flag +$(eval $(call assert_boolean,ERRATA_N1_1220197)) +$(eval $(call add_define,ERRATA_N1_1220197)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 335b3c79c79dcfc04e9776ce2e21c3b16aa6febf Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:42:02 -0500 Subject: [PATCH 06/10] Workaround for Neoverse N1 erratum 1257314 Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 3 +++ lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 47 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index ee8da1767..14dfe9580 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -243,6 +243,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 952ae6ebe..0e9ddb8fe 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -48,6 +48,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 0e7b8e8cc..19b21a57e 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -211,6 +211,33 @@ func check_errata_1220197 b cpu_rev_var_ls endfunc check_errata_1220197 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1257314 + * This applies to revision <=r3p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1257314_wa + /* Compare x0 against revision r3p0 */ + mov x17, x30 + bl check_errata_1257314 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 + msr NEOVERSE_N1_CPUACTLR3_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1257314_wa + +func check_errata_1257314 + /* Applies to <=r3p0 */ + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1257314 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -284,6 +311,11 @@ func neoverse_n1_reset_func bl errata_n1_1220197_wa #endif +#if ERRATA_N1_1257314 + mov x0, x18 + bl errata_n1_1257314_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -351,6 +383,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 + report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index bb53dad0a..c4769d9e7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -258,6 +258,10 @@ ERRATA_N1_1207823 ?=0 # only to revision <= r2p0 of the Neoverse N1 cpu. ERRATA_N1_1220197 ?=0 +# Flag to apply erratum 1257314 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Neoverse N1 cpu. +ERRATA_N1_1257314 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -471,6 +475,10 @@ $(eval $(call add_define,ERRATA_N1_1207823)) $(eval $(call assert_boolean,ERRATA_N1_1220197)) $(eval $(call add_define,ERRATA_N1_1220197)) +# Process ERRATA_N1_1257314 flag +$(eval $(call assert_boolean,ERRATA_N1_1257314)) +$(eval $(call add_define,ERRATA_N1_1257314)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 411f4959b45b7a072b567dadf33b110936f14f32 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:44:58 -0500 Subject: [PATCH 07/10] Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 1 + lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 45 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 14dfe9580..1ed7cebe7 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -246,6 +246,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 0e9ddb8fe..8f0ecf2b8 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -38,6 +38,7 @@ #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 19b21a57e..600457573 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -238,6 +238,33 @@ func check_errata_1257314 b cpu_rev_var_ls endfunc check_errata_1257314 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1262606 + * This applies to revision <=r3p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1262606_wa + /* Compare x0 against revision r3p0 */ + mov x17, x30 + bl check_errata_1262606 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 + msr NEOVERSE_N1_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1262606_wa + +func check_errata_1262606 + /* Applies to <=r3p0 */ + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262606 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -316,6 +343,11 @@ func neoverse_n1_reset_func bl errata_n1_1257314_wa #endif +#if ERRATA_N1_1262606 + mov x0, x18 + bl errata_n1_1262606_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -384,6 +416,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 + report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index c4769d9e7..befb45eb0 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -262,6 +262,10 @@ ERRATA_N1_1220197 ?=0 # only to revision <= r3p0 of the Neoverse N1 cpu. ERRATA_N1_1257314 ?=0 +# Flag to apply erratum 1262606 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Neoverse N1 cpu. +ERRATA_N1_1262606 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -479,6 +483,10 @@ $(eval $(call add_define,ERRATA_N1_1220197)) $(eval $(call assert_boolean,ERRATA_N1_1257314)) $(eval $(call add_define,ERRATA_N1_1257314)) +# Process ERRATA_N1_1262606 flag +$(eval $(call assert_boolean,ERRATA_N1_1262606)) +$(eval $(call add_define,ERRATA_N1_1262606)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 11c48370bd8c1dfdf5221a073a26615904c94413 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:47:30 -0500 Subject: [PATCH 08/10] Workaround for Neoverse N1 erratum 1262888 Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ include/lib/cpus/aarch64/neoverse_n1.h | 1 + lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 45 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 1ed7cebe7..91032c4de 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -249,6 +249,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 8f0ecf2b8..f90aa2ea4 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -31,6 +31,7 @@ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 600457573..d5f224738 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -265,6 +265,33 @@ func check_errata_1262606 b cpu_rev_var_ls endfunc check_errata_1262606 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1262888 + * This applies to revision <=r3p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1262888_wa + /* Compare x0 against revision r3p0 */ + mov x17, x30 + bl check_errata_1262888 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUECTLR_EL1 + orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT + msr NEOVERSE_N1_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1262888_wa + +func check_errata_1262888 + /* Applies to <=r3p0 */ + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262888 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -348,6 +375,11 @@ func neoverse_n1_reset_func bl errata_n1_1262606_wa #endif +#if ERRATA_N1_1262888 + mov x0, x18 + bl errata_n1_1262888_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -417,6 +449,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 + report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index befb45eb0..2f13696d6 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -266,6 +266,10 @@ ERRATA_N1_1257314 ?=0 # only to revision <= r3p0 of the Neoverse N1 cpu. ERRATA_N1_1262606 ?=0 +# Flag to apply erratum 1262888 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Neoverse N1 cpu. +ERRATA_N1_1262888 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -487,6 +491,10 @@ $(eval $(call add_define,ERRATA_N1_1257314)) $(eval $(call assert_boolean,ERRATA_N1_1262606)) $(eval $(call add_define,ERRATA_N1_1262606)) +# Process ERRATA_N1_1262888 flag +$(eval $(call assert_boolean,ERRATA_N1_1262888)) +$(eval $(call add_define,ERRATA_N1_1262888)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 4d8801fe5aa0d26ab3df42d31f0e7129209d301b Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:49:01 -0500 Subject: [PATCH 09/10] Workaround for Neoverse N1 erratum 1275112 Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ lib/cpus/aarch64/neoverse_n1.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 3 files changed, 44 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 91032c4de..d3fe89d62 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -252,6 +252,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index d5f224738..cffdf9eb6 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -292,6 +292,33 @@ func check_errata_1262888 b cpu_rev_var_ls endfunc check_errata_1262888 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #1275112 + * This applies to revision <=r3p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1275112_wa + /* Compare x0 against revision r3p0 */ + mov x17, x30 + bl check_errata_1275112 + cbz x0, 1f + mrs x1, NEOVERSE_N1_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 + msr NEOVERSE_N1_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_n1_1275112_wa + +func check_errata_1275112 + /* Applies to <=r3p0 */ + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1275112 + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1315703. * This applies to revision <= r3p0 of Neoverse N1. @@ -380,6 +407,11 @@ func neoverse_n1_reset_func bl errata_n1_1262888_wa #endif +#if ERRATA_N1_1275112 + mov x0, x18 + bl errata_n1_1275112_wa +#endif + #if ERRATA_N1_1315703 mov x0, x18 bl errata_n1_1315703_wa @@ -450,6 +482,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 + report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 2f13696d6..260402351 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -270,6 +270,10 @@ ERRATA_N1_1262606 ?=0 # only to revision <= r3p0 of the Neoverse N1 cpu. ERRATA_N1_1262888 ?=0 +# Flag to apply erratum 1275112 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Neoverse N1 cpu. +ERRATA_N1_1275112 ?=0 + # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. ERRATA_N1_1315703 ?=1 @@ -495,6 +499,10 @@ $(eval $(call add_define,ERRATA_N1_1262606)) $(eval $(call assert_boolean,ERRATA_N1_1262888)) $(eval $(call add_define,ERRATA_N1_1262888)) +# Process ERRATA_N1_1275112 flag +$(eval $(call assert_boolean,ERRATA_N1_1275112)) +$(eval $(call add_define,ERRATA_N1_1275112)) + # Process ERRATA_N1_1315703 flag $(eval $(call assert_boolean,ERRATA_N1_1315703)) $(eval $(call add_define,ERRATA_N1_1315703)) From 7d6f751867a6c778280d931857663a3218251609 Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Thu, 27 Jun 2019 11:03:25 -0500 Subject: [PATCH 10/10] Removing redundant ISB instructions Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister --- lib/cpus/aarch64/neoverse_n1.S | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index cffdf9eb6..b143a2e7b 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -43,7 +43,6 @@ func errata_n1_1043202_wa msr CPUPMR_EL3, x0 ldr x0, =0x800200071 msr CPUPCR_EL3, x0 - isb 1: ret x17 endfunc errata_n1_1043202_wa @@ -69,7 +68,6 @@ func neoverse_n1_disable_speculative_loads /* Disable speculative loads */ msr SSBS, xzr - isb 1: ret @@ -91,7 +89,6 @@ func errata_n1_1073348_wa mrs x1, NEOVERSE_N1_CPUACTLR_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 msr NEOVERSE_N1_CPUACTLR_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1073348_wa @@ -118,7 +115,6 @@ func errata_n1_1130799_wa mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1130799_wa @@ -146,7 +142,6 @@ func errata_n1_1165347_wa orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1165347_wa @@ -173,7 +168,6 @@ func errata_n1_1207823_wa mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1207823_wa @@ -200,7 +194,6 @@ func errata_n1_1220197_wa mrs x1, NEOVERSE_N1_CPUECTLR_EL1 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK msr NEOVERSE_N1_CPUECTLR_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1220197_wa @@ -227,7 +220,6 @@ func errata_n1_1257314_wa mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1257314_wa @@ -254,7 +246,6 @@ func errata_n1_1262606_wa mrs x1, NEOVERSE_N1_CPUACTLR_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 msr NEOVERSE_N1_CPUACTLR_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1262606_wa @@ -281,7 +272,6 @@ func errata_n1_1262888_wa mrs x1, NEOVERSE_N1_CPUECTLR_EL1 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT msr NEOVERSE_N1_CPUECTLR_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1262888_wa @@ -308,7 +298,6 @@ func errata_n1_1275112_wa mrs x1, NEOVERSE_N1_CPUACTLR_EL1 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 msr NEOVERSE_N1_CPUACTLR_EL1, x1 - isb 1: ret x17 endfunc errata_n1_1275112_wa @@ -336,7 +325,6 @@ func errata_n1_1315703_wa mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 - isb 1: ret x17 @@ -422,24 +410,22 @@ func neoverse_n1_reset_func mrs x0, actlr_el3 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT msr actlr_el3, x0 - isb /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ mrs x0, actlr_el2 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT msr actlr_el2, x0 - isb /* Enable group0 counters */ mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK msr CPUAMCNTENSET_EL0, x0 - isb #endif #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif + isb ret x19 endfunc neoverse_n1_reset_func