feat(ls1046ardb): add ls1046ardb board support
The LS1046A reference design board (RDB) is a high-performance computing, evaluation, and development platform that supports the Layerscape LS1046A architecture processor. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ib7a01b309e0b0acc7f38e22b138e9e181dff244a
This commit is contained in:
Jiafei Pan
parent
cc708597fa
commit
bb52f7560b
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <errata.h>
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_2100 = {
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.cs[0].config = U(0x80040322),
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.cs[0].bnds = U(0x1FF),
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.cs[1].config = U(0x80000322),
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.cs[1].bnds = U(0x1FF),
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.sdram_cfg[0] = U(0xE5004000),
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.sdram_cfg[1] = U(0x401151),
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.timing_cfg[0] = U(0xD1770018),
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.timing_cfg[1] = U(0xF2FC9245),
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.timing_cfg[2] = U(0x594197),
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.timing_cfg[3] = U(0x2101100),
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.timing_cfg[4] = U(0x220002),
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.timing_cfg[5] = U(0x5401400),
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.timing_cfg[7] = U(0x26600000),
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.timing_cfg[8] = U(0x5446A00),
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.dq_map[0] = U(0x32C57554),
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.dq_map[1] = U(0xD4BB0BD4),
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.dq_map[2] = U(0x2EC2F554),
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.dq_map[3] = U(0xD95D4001),
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.sdram_mode[0] = U(0x3010631),
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.sdram_mode[1] = U(0x100200),
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.sdram_mode[9] = U(0x8400000),
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.sdram_mode[8] = U(0x500),
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.sdram_mode[2] = U(0x10631),
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.sdram_mode[3] = U(0x100200),
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.sdram_mode[10] = U(0x400),
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.sdram_mode[11] = U(0x8400000),
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.sdram_mode[4] = U(0x10631),
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.sdram_mode[5] = U(0x100200),
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.sdram_mode[12] = U(0x400),
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.sdram_mode[13] = U(0x8400000),
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.sdram_mode[6] = U(0x10631),
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.sdram_mode[7] = U(0x100200),
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.sdram_mode[14] = U(0x400),
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.sdram_mode[15] = U(0x8400000),
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.interval = U(0x1FFE07FF),
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.zq_cntl = U(0x8A090705),
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.clk_cntl = U(0x2000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xC1),
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.wrlvl_cntl[0] = U(0x86750609),
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.wrlvl_cntl[1] = U(0xA0B0C0D),
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.wrlvl_cntl[2] = U(0xF10110E),
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};
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const struct ddr_cfg_regs static_1800 = {
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.cs[0].config = U(0x80040322),
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.cs[0].bnds = U(0x1FF),
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.cs[1].config = U(0x80000322),
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.cs[1].bnds = U(0x1FF),
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.sdram_cfg[0] = U(0xE5004000),
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.sdram_cfg[1] = U(0x401151),
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.timing_cfg[0] = U(0x91660018),
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.timing_cfg[1] = U(0xDDD82045),
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.timing_cfg[2] = U(0x512153),
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.timing_cfg[3] = U(0x10E1100),
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.timing_cfg[4] = U(0x220002),
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.timing_cfg[5] = U(0x4401400),
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.timing_cfg[7] = U(0x14400000),
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.timing_cfg[8] = U(0x3335900),
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.dq_map[0] = U(0x32C57554),
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.dq_map[1] = U(0xD4BB0BD4),
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.dq_map[2] = U(0x2EC2F554),
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.dq_map[3] = U(0xD95D4001),
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.sdram_mode[0] = U(0x3010421),
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.sdram_mode[1] = U(0x80200),
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.sdram_mode[9] = U(0x4400000),
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.sdram_mode[8] = U(0x500),
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.sdram_mode[2] = U(0x10421),
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.sdram_mode[3] = U(0x80200),
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.sdram_mode[10] = U(0x400),
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.sdram_mode[11] = U(0x4400000),
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.sdram_mode[4] = U(0x10421),
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.sdram_mode[5] = U(0x80200),
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.sdram_mode[12] = U(0x400),
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.sdram_mode[13] = U(0x4400000),
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.sdram_mode[6] = U(0x10421),
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.sdram_mode[7] = U(0x80200),
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.sdram_mode[14] = U(0x400),
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.sdram_mode[15] = U(0x4400000),
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.interval = U(0x1B6C06DB),
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.zq_cntl = U(0x8A090705),
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.clk_cntl = U(0x2000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xC1),
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.wrlvl_cntl[0] = U(0x86750607),
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.wrlvl_cntl[1] = U(0x8090A0B),
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.wrlvl_cntl[2] = U(0xD0E0F0C),
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};
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const struct ddr_cfg_regs static_1600 = {
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.cs[0].config = U(0x80040322),
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.cs[0].bnds = U(0x1FF),
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.cs[1].config = U(0x80000322),
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.cs[1].bnds = U(0x1FF),
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.sdram_cfg[0] = U(0xE5004000),
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.sdram_cfg[1] = U(0x401151),
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.sdram_cfg[2] = U(0x0),
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.timing_cfg[0] = U(0x91550018),
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.timing_cfg[1] = U(0xBAB48E44),
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.timing_cfg[2] = U(0x490111),
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.timing_cfg[3] = U(0x10C1000),
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.timing_cfg[4] = U(0x220002),
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.timing_cfg[5] = U(0x3401400),
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.timing_cfg[6] = U(0x0),
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.timing_cfg[7] = U(0x13300000),
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.timing_cfg[8] = U(0x1224800),
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.timing_cfg[9] = U(0x0),
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.dq_map[0] = U(0x32C57554),
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.dq_map[1] = U(0xD4BB0BD4),
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.dq_map[2] = U(0x2EC2F554),
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.dq_map[3] = U(0xD95D4001),
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.sdram_mode[0] = U(0x3010211),
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.sdram_mode[1] = U(0x0),
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.sdram_mode[9] = U(0x400000),
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.sdram_mode[8] = U(0x500),
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.sdram_mode[2] = U(0x10211),
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.sdram_mode[3] = U(0x0),
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.sdram_mode[10] = U(0x400),
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.sdram_mode[11] = U(0x400000),
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.sdram_mode[4] = U(0x10211),
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.sdram_mode[5] = U(0x0),
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.sdram_mode[12] = U(0x400),
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.sdram_mode[13] = U(0x400000),
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.sdram_mode[6] = U(0x10211),
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.sdram_mode[7] = U(0x0),
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.sdram_mode[14] = U(0x400),
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.sdram_mode[15] = U(0x400000),
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.interval = U(0x18600618),
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.zq_cntl = U(0x8A090705),
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.ddr_sr_cntr = U(0x0),
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.clk_cntl = U(0x2000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xC1),
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.wrlvl_cntl[0] = U(0x86750607),
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.wrlvl_cntl[1] = U(0x8090A0B),
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.wrlvl_cntl[2] = U(0xD0E0F0C),
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};
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struct static_table {
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unsigned long rate;
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const struct ddr_cfg_regs *regs;
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};
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const struct static_table table[] = {
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{1600, &static_1600},
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{1800, &static_1800},
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{2100, &static_2100},
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};
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long long board_static_ddr(struct ddr_info *priv)
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{
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const unsigned long clk = priv->clk / 1000000;
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long long size = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(table); i++) {
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if (table[i].rate >= clk) {
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break;
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}
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}
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if (i < ARRAY_SIZE(table)) {
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VERBOSE("Found static setting for rate %ld\n", table[i].rate);
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memcpy(&priv->ddr_reg, table[i].regs,
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sizeof(struct ddr_cfg_regs));
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size = 0x200000000UL;
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} else {
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ERROR("Not static settings for rate %ld\n", clk);
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}
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return size;
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}
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#else /* ifndef CONFIG_STATIC_DDR */
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static const struct rc_timing rce[] = {
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{U(1600), U(8), U(7)},
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{U(1867), U(8), U(7)},
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{U(2134), U(8), U(9)},
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{}
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};
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static const struct board_timing udimm[] = {
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{U(0x04), rce, U(0x01020304), U(0x06070805)},
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{U(0x1f), rce, U(0x01020304), U(0x06070805)},
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};
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int ddr_board_options(struct ddr_info *priv)
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{
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int ret;
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struct memctl_opt *popts = &priv->opt;
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if (popts->rdimm) {
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debug("RDIMM parameters not set.\n");
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return -EINVAL;
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}
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ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
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if (ret != 0) {
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return ret;
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}
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popts->wrlvl_override = U(1);
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popts->wrlvl_sample = U(0x0); /* 32 clocks */
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popts->cpo_sample = U(0x61);
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_TRAIN_EN |
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DDR_CDR2_VREF_RANGE_2;
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popts->bstopre = U(0);
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return 0;
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}
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#endif /* ifdef CONFIG_STATIC_DDR */
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long long init_ddr(void)
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{
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int spd_addr[] = {NXP_SPD_EEPROM0};
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struct ddr_info info;
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struct sysinfo sys;
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long long dram_size;
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zeromem(&sys, sizeof(sys));
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if (get_clocks(&sys)) {
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ERROR("System clocks are not set\n");
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assert(0);
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}
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(struct ddr_info));
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info.num_ctlrs = U(1);
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info.dimm_on_ctlr = U(1);
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info.clk = get_ddr_freq(&sys, 0);
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info.spd_addr = spd_addr;
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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dram_size = dram_init(&info);
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if (dram_size < 0) {
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ERROR("DDR init failed.\n");
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}
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#ifdef ERRATA_SOC_A008850
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erratum_a008850_post();
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#endif
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return dram_size;
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}
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DEF_H
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#define PLAT_DEF_H
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#include <arch.h>
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/*
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* Required without TBBR.
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* To include the defines for DDR PHY Images.
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*/
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#include <tbbr_img_def.h>
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#include "policy.h"
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#include <soc.h>
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#define NXP_SPD_EEPROM0 0x51
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#define NXP_SYSCLK_FREQ 100000000
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#define NXP_DDRCLK_FREQ 100000000
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/* UART related definition */
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#define NXP_CONSOLE_ADDR NXP_UART_ADDR
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#define NXP_CONSOLE_BAUDRATE 115200
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL2)
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#if defined(TRUSTED_BOARD_BOOT)
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#define PLATFORM_STACK_SIZE 0x2000
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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/* SD block buffer */
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#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
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#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
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/* IO defines as needed by IO driver framework */
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define MAX_IO_HANDLES U(4)
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/*
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* FIP image defines - Offset at which FIP Image would be present
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* Image would include Bl31 , Bl33 and Bl32 (optional)
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*/
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#ifdef POLICY_FUSE_PROVISION
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#define MAX_FIP_DEVICES U(2)
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#endif
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#ifndef MAX_FIP_DEVICES
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#define MAX_FIP_DEVICES U(1)
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#endif
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/*
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* ID of the secure physical generic timer interrupt used by the BL32.
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*/
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#define BL32_IRQ_SEC_PHY_TIMER 29
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_LS_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_LS_G0_IRQ_PROPS(grp)
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#endif /* PLAT_DEF_H */
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/*
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat_common.h>
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#pragma weak board_enable_povdd
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#pragma weak board_disable_povdd
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bool board_enable_povdd(void)
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{
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#ifdef CONFIG_POVDD_ENABLE
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return true;
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#else
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return false;
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#endif
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}
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bool board_disable_povdd(void)
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{
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#ifdef CONFIG_POVDD_ENABLE
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return true;
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#else
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return false;
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#endif
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}
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@ -0,0 +1,38 @@
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#
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# Copyright 2018-2022 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# board-specific build parameters
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BOOT_MODE ?= qspi
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BOARD := ls1046ardb
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POVDD_ENABLE := no
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# DDR Compilation Configs
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NUM_OF_DDRC := 1
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DDRC_NUM_DIMM := 1
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DDRC_NUM_CS := 4
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DDR_ECC_EN := yes
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CONFIG_STATIC_DDR := 0
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# On-Board Flash Details
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QSPI_FLASH_SZ := 0x20000000
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NOR_FLASH_SZ := 0x20000000
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# Platform specific features.
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WARM_BOOT := no
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# Adding Platform files build files
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BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
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${BOARD_PATH}/platform.c
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SUPPORTED_BOOT_MODE := qspi \
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sd \
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emmc
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# Adding platform board build info
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include plat/nxp/common/plat_make_helper/plat_common_def.mk
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# Adding SoC build info
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include plat/nxp/soc-ls1046a/soc.mk
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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|
||||
#include <plat_def.h>
|
||||
#include <plat_default_def.h>
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
#endif /* POLICY_H */
|
||||
Loading…
Reference in New Issue