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Tegra186: SiP calls to interact with the MCE driver 

This patch adds the new SiP SMC calls to allow the NS world to
interact with the MCE hardware block on Tegra186 chips.

Change-Id: I79c6b9f76d68a87abd57a940613ec070562d2eac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-09-09 11:33:08 +05:30
parent 7808b06b99
commit bb844c1f0d
1 changed files with 54 additions and 53 deletions
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107
plat/nvidia/tegra/soc/t186/plat_sip_calls.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -35,80 +35,81 @@
#include <context_mgmt.h>
#include <debug.h>
#include <errno.h>
#include <memctrl.h>
#include <mce.h>
#include <runtime_svc.h>
#include <t18x_ari.h>
#include <tegra_private.h>
/*******************************************************************************
* Tegra186 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03
#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04
#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05
#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06
#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07
#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08
#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09
#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A
#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B
#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C
#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D
#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E
#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F
/*******************************************************************************
* This function is responsible for handling all SiP calls from the NS world
* This function is responsible for handling all T186 SiP calls
******************************************************************************/
uint64_t tegra186_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags)
int plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags)
{
uint32_t ns;
int err;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
if (!ns)
SMC_RET1(handle, SMC_UNK);
int mce_ret;
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/*
* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
* 0x82FFFFFF SiP SMC space
*/
case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
case TEGRA_SIP_MCE_CMD_CC3_CTRL:
case TEGRA_SIP_MCE_CMD_ECHO_DATA:
case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
/* clean up the high bits */
x1 = (uint32_t)x1;
x2 = (uint32_t)x2;
smc_fid &= MCE_CMD_MASK;
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
if (err)
SMC_RET1(handle, err);
/* execute the command and store the result */
mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
/*
* Check if Video Memory is aligned to 1MB.
*/
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
SMC_RET1(handle, 0);
break;
return 0;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}
SMC_RET1(handle, SMC_UNK);
return -ENOTSUP;
}
/* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC(
tegra186_sip_fast,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
tegra186_sip_handler
);