From bc1a573d5519f121cb872fce1d88fe2e0db07b2c Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Wed, 5 Aug 2020 22:12:23 +0800 Subject: [PATCH] fix(intel): refactor NOC header Refactor NOC header to be shareable across both Stratix 10 and Agilex platforms. This patch also removes redundant NOC declarations in system manager header file. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a Signed-off-by: Jit Loon Lim --- plat/intel/soc/agilex/include/agilex_noc.h | 2 +- .../soc/agilex/include/socfpga_plat_def.h | 2 + plat/intel/soc/common/include/socfpga_noc.h | 82 +++++++++++++++++++ .../common/include/socfpga_system_manager.h | 61 -------------- .../soc/common/soc/socfpga_system_manager.c | 11 +-- .../soc/stratix10/include/socfpga_plat_def.h | 3 +- 6 files changed, 93 insertions(+), 68 deletions(-) create mode 100644 plat/intel/soc/common/include/socfpga_noc.h diff --git a/plat/intel/soc/agilex/include/agilex_noc.h b/plat/intel/soc/agilex/include/agilex_noc.h index 22db3e28f..9aba3c33b 100644 --- a/plat/intel/soc/agilex/include/agilex_noc.h +++ b/plat/intel/soc/agilex/include/agilex_noc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 9c87e450d..6a5cf9b32 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -19,6 +19,8 @@ #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 /* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 + #define SOCFPGA_MMC_REG_BASE 0xff808000 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h new file mode 100644 index 000000000..66d0ee72a --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_noc.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_NOC_H +#define SOCFPGA_NOC_H + +/* Macros */ +#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ + + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) + +#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) + +#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) + +/* L3 Interconnect Register Map */ +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 + +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 + +/* CCU NOC Register Map */ + +#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688 +#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628 + +#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) +#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) + +#endif + diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index 2b13f1fd3..b037cc61c 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -58,67 +58,6 @@ #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + (SOCFPGA_SYSMGR_##_reg)) -#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ - + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) - -#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ - + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) - -/* L3 Interconnect Register Map */ -#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 -#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 -#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c -#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 -#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 -#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 -#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c -#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 -#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 -#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c -#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 - -#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 -#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 - -#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c index a64053ca6..ee7c7846d 100644 --- a/plat/intel/soc/common/soc/socfpga_system_manager.c +++ b/plat/intel/soc/common/soc/socfpga_system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #include #include +#include "socfpga_noc.h" #include "socfpga_system_manager.h" void enable_nonsecure_access(void) @@ -92,10 +93,10 @@ void enable_ns_peripheral_access(void) mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 - mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); - mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03); - - mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); + mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); + mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0), + SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK); #endif } diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index b84a56749..2defeb9f4 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -1,5 +1,4 @@ /* - * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -19,6 +18,8 @@ #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 /* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 + #define SOCFPGA_MMC_REG_BASE 0xff808000 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000