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fix(plat/xilinx/versal): resolve misra R15.7 

MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated with an else statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iea32e32b5683f7accd7fac8d557957f05ed0f5c5
This commit is contained in:
Abhyuday Godhasara 2021-08-11 02:52:35 -07:00
parent b9fa2d9fc1
commit bc2637e379
1 changed files with 5 additions and 0 deletions
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5
plat/xilinx/versal/bl31_versal_setup.c
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@ -83,7 +83,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if (rc == 0) {
panic();
}
} else {
NOTICE("BL31: Did not register for any console.\n");
}
/* Initialize the platform config for future decision making */
versal_config_setup();
/* There are no parameters from BL2 if BL31 is a reset vector */
@ -111,6 +114,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
bl31_set_default_config();
} else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
} else {
ERROR("BL31: Error during fsbl-atf handover %d.\n", ret);
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);