From 3d9f726438bea5fe0eb2a88b54d2c6c29b026b93 Mon Sep 17 00:00:00 2001 From: Hadi Asyrafi Date: Wed, 16 Oct 2019 13:02:22 +0800 Subject: [PATCH] intel: Fix memory calibration Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 --- .../intel/soc/agilex/soc/agilex_memory_controller.c | 7 +++---- .../intel/soc/stratix10/soc/s10_memory_controller.c | 13 ++++++------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c index 5f3cae7be..2aabe87cc 100644 --- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c +++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c @@ -20,9 +20,8 @@ #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 #define TIMEOUT_EMIF_CALIBRATION 1000 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -125,7 +124,7 @@ static int mem_calibration(void) data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - mdelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index ed06f5498..cb4525149 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -22,10 +22,9 @@ #define MAX_MEM_CAL_RETRY 3 #define PRE_CALIBRATION_DELAY 1 #define POST_CALIBRATION_DELAY 1 -#define TIMEOUT_EMIF_CALIBRATION 100 -#define CLEAR_EMIF_DELAY 50000 -#define CLEAR_EMIF_TIMEOUT 0x100000 -#define TIMEOUT_INT_RESP 10000 +#define TIMEOUT_EMIF_CALIBRATION 1000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t)) @@ -128,13 +127,13 @@ static int mem_calibration(void) data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) break; - udelay(1); + udelay(500); } while (++timeout < TIMEOUT_EMIF_CALIBRATION); if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { status = clear_emif(); - if (status) - ERROR("Failed to clear Emif\n"); + if (status) + ERROR("Failed to clear Emif\n"); } else { break; }