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rcar_gen3: plat: Fix BL2 size check 

Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut 2018-12-26 15:57:08 +01:00
parent fc181c3b2c
commit bc5fabd813
3 changed files with 6 additions and 6 deletions
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2
plat/renesas/rcar/bl2_plat_setup.c
View File

@ -899,7 +899,7 @@ void bl2_el3_plat_arch_setup(void)
#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE,
RCAR_SYSRAM_LIMIT - BL2_BASE,
BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT

8
plat/renesas/rcar/include/platform_def.h
View File

@ -104,16 +104,16 @@
* size plus a little space for growth. */
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if RCAR_LSI == RCAR_E3
#define RCAR_SYSRAM_LIMIT U(0xE6320000)
#define BL2_LIMIT U(0xE6320000)
#else
#define RCAR_SYSRAM_LIMIT U(0xE6360000)
#define BL2_LIMIT U(0xE6360000)
#endif
#define BL2_BASE U(0xE6304000)
#if RCAR_LSI == RCAR_E3
#define BL2_LIMIT U(0xE6318000)
#define BL2_IMAGE_LIMIT U(0xE6318000)
#else
#define BL2_LIMIT U(0xE632E800)
#define BL2_IMAGE_LIMIT U(0xE632E800)
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)

2
plat/renesas/rcar/include/rcar_def.h
View File

@ -24,7 +24,7 @@
#define DEVICE_RCAR_SIZE U(0x00300000)
#define DEVICE_RCAR_BASE2 U(0xE6360000)
#define DEVICE_RCAR_SIZE2 U(0x19CA0000)
#define DEVICE_SRAM_BASE U(0xE6310000)
#define DEVICE_SRAM_BASE U(0xE6300000)
#define DEVICE_SRAM_SIZE U(0x00002000)
#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
#define DEVICE_SRAM_STACK_SIZE U(0x00001000)