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Merge changes from topic "rdevans" into integration 

* changes:
  doc: Update list of supported FVP platforms
  board/rdn2: add board support for rdn2 platform
  plat/arm/sgi: adapt to changes in memory map
  plat/arm/sgi: add platform id value for rdn2 platform
  plat/arm/sgi: platform definitions for upcoming platforms
  plat/arm/sgi: refactor header file inclusions
  plat/arm/sgi: refactor the inclusion of memory mapping
This commit is contained in:
Madhukar Pappireddy 2020-12-11 15:21:54 +00:00 committed by TrustedFirmware Code Review
parent 2736aca597 7b24e48a46
commit bd054fd66b
31 changed files with 693 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
docs/plat/arm/fvp/index.rst
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@ -50,6 +50,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
- ``FVP_RD_N1_edge`` (Version 11.10 build 36)
- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
- ``FVP_RD_Daniel`` (Version 11.10 build 36)
- ``FVP_RD_N2`` (Version 11.13 build 10)
- ``FVP_TC0`` (Version 0.0 build 6114)
- ``Foundation_Platform``

2
plat/arm/board/rddaniel/include/platform_def.h
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@ -9,7 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)

2
plat/arm/board/rddaniel/platform.mk
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@ -14,6 +14,8 @@ PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIEL_BASE}/rddaniel_err.c

2
plat/arm/board/rddanielxlr/include/platform_def.h
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@ -8,7 +8,7 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(4)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)

2
plat/arm/board/rddanielxlr/platform.mk
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@ -15,6 +15,8 @@ PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIELXLR_BASE}/rddanielxlr_err.c

2
plat/arm/board/rddanielxlr/rddanielxlr_plat.c
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@ -8,7 +8,7 @@
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)

2
plat/arm/board/rde1edge/include/platform_def.h
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@ -9,7 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)

2
plat/arm/board/rde1edge/platform.mk
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@ -12,6 +12,8 @@ PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDE1EDGE_BASE}/rde1edge_err.c

2
plat/arm/board/rdn1edge/include/platform_def.h
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@ -9,7 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)

2
plat/arm/board/rdn1edge/platform.mk
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@ -15,6 +15,8 @@ PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDN1EDGE_BASE}/rdn1edge_err.c

2
plat/arm/board/rdn1edge/rdn1edge_plat.c
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@ -8,7 +8,7 @@
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)

27
plat/arm/board/rdn2/fdts/rdn2_fw_config.dts Normal file
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@ -0,0 +1,27 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
/dts-v1/;
/ {
dtb-registry {
compatible = "fconf,dyn_cfg-dtb_registry";
tb_fw-config {
load-address = <0x0 0x4001300>;
max-size = <0x200>;
id = <TB_FW_CONFIG_ID>;
};
nt_fw-config {
load-address = <0x0 0xFEF00000>;
max-size = <0x0100000>;
id = <NT_FW_CONFIG_ID>;
};
};
};

22
plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,rd-n2";
/*
* Place holder for system-id node with default values. The
* value of platform-id and config-id will be set to the
* correct values during the BL2 stage of boot.
*/
system-id {
platform-id = <0x0>;
config-id = <0x0>;
multi-chip-mode = <0x0>;
};
};

28
plat/arm/board/rdn2/fdts/rdn2_tb_fw_config.dts Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
tb_fw-config {
compatible = "arm,tb_fw";
/* Disable authentication for development */
disable_auth = <0x0>;
/*
* The following two entries are placeholders for Mbed TLS
* heap information. The default values don't matter since
* they will be overwritten by BL1.
* In case of having shared Mbed TLS heap between BL1 and BL2,
* BL1 will populate these two properties with the respective
* info about the shared heap. This info will be available for
* BL2 in order to locate and re-use the heap.
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
};

65
plat/arm/board/rdn2/include/platform_def.h Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_soc_platform_def_v2.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x2A920000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x10820000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
#define TZC400_COUNT U(8)
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
(n * TZC400_OFFSET))
#define TZC_NSAID_ALL_AP U(0)
#define TZC_NSAID_PCI U(1)
#define TZC_NSAID_HDLCD0 U(2)
#define TZC_NSAID_CLCD U(7)
#define TZC_NSAID_AP U(9)
#define TZC_NSAID_VIRTIO U(15)
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
#endif /* PLATFORM_DEF_H */

59
plat/arm/board/rdn2/platform.mk Normal file
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@ -0,0 +1,59 @@
# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# RD-N2 platform uses GIC-Clayton which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
include plat/arm/css/sgi/sgi-common.mk
RDN2_BASE = plat/arm/board/rdn2
PLAT_INCLUDES += -I${RDN2_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDN2_BASE}/rdn2_err.c
BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
${RDN2_BASE}/rdn2_security.c \
${RDN2_BASE}/rdn2_err.c \
lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDN2_BASE}/rdn2_plat.c \
${RDN2_BASE}/rdn2_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
endif
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0

17
plat/arm/board/rdn2/rdn2_err.c Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* rdn2 error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
while (1) {
wfi();
}
}

31
plat/arm/board/rdn2/rdn2_plat.c Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#include <sgi_plat.h>
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
& SID_SYSTEM_ID_PART_NUM_MASK;
}
unsigned int plat_arm_sgi_get_config_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
}
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
SID_MULTI_CHIP_MODE_MASK) >>
SID_MULTI_CHIP_MODE_SHIFT;
}
void bl31_platform_setup(void)
{
sgi_bl31_common_platform_setup();
}

25
plat/arm/board/rdn2/rdn2_security.c Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
{}
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
int i;
for (i = 0; i < TZC400_COUNT; i++)
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}

62
plat/arm/board/rdn2/rdn2_topology.c Normal file
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@ -0,0 +1,62 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_n2_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
};
/*******************************************************************************
* This function returns the topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return rd_n2_pd_tree_desc;
}
/*******************************************************************************
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
};

26
plat/arm/board/rdn2/rdn2_trusted_boot.c Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* Return the ROTPK hash in the following ASN.1 structure in DER format:
*
* AlgorithmIdentifier ::= SEQUENCE {
* algorithm OBJECT IDENTIFIER,
* parameters ANY DEFINED BY algorithm OPTIONAL
* }
*
* DigestInfo ::= SEQUENCE {
* digestAlgorithm AlgorithmIdentifier,
* digest OCTET STRING
* }
*/
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
unsigned int *flags)
{
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
}

2
plat/arm/board/sgi575/include/platform_def.h
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@ -9,7 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)

2
plat/arm/board/sgi575/platform.mk
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@ -12,6 +12,8 @@ PLAT_INCLUDES += -I${SGI575_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${SGI575_BASE}/sgi575_err.c

3
plat/arm/css/sgi/include/sgi_base_platform_def.h
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@ -9,12 +9,9 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/board_css_def.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/css/common/css_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \

194
plat/arm/css/sgi/include/sgi_soc_css_def_v2.h Normal file
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@ -0,0 +1,194 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_SOC_CSS_DEF_V2_H
#define SGI_SOC_CSS_DEF_V2_H
#include <lib/utils_def.h>
#include <plat/common/common_def.h>
/*
* Definitions common to all ARM CSS SoCs
*/
/* Following covers ARM CSS SoC Peripherals */
#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
/* PL011 UART related constants */
#define SOC_CSS_UART1_BASE UL(0x0ef80000)
#define SOC_CSS_UART0_BASE UL(0x0ef70000)
/* Memory controller */
#define SOC_MEMCNTRL_BASE UL(0x10000000)
#define SOC_MEMCNTRL_SIZE UL(0x10000000)
#define SOC_CSS_UART0_CLK_IN_HZ UL(7372800)
#define SOC_CSS_UART1_CLK_IN_HZ UL(7372800)
/* SoC NIC-400 Global Programmers View (GPV) */
#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
#define SOC_CSS_NIC400_USB_EHCI U(0)
#define SOC_CSS_NIC400_TLX_MASTER U(1)
#define SOC_CSS_NIC400_USB_OHCI U(2)
#define SOC_CSS_NIC400_PL354_SMC U(3)
/*
* The apb4_bridge controls access to:
* - the PCIe configuration registers
* - the MMU units for USB, HDLCD and DMA
*/
#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
/* Non-volatile counters */
#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
#define TFW_NVCTR_SIZE U(4)
#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
#define NTFW_CTR_SIZE U(4)
/* Keys */
#define SOC_KEYS_BASE UL(0x0EE80000)
#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
#define TZ_PUB_KEY_HASH_SIZE U(32)
#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
#define HU_KEY_SIZE U(16)
#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
#define END_KEY_SIZE U(32)
#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
SOC_SYSTEM_PERIPH_BASE, \
SOC_SYSTEM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \
SOC_MEMCNTRL_BASE, \
SOC_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
/*
* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
*/
#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
/*
* Required platform porting definitions common to all ARM CSS SoCs
*/
/* 2MB used for SCP DDR retraining */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000)
/* V2M motherboard system registers & offsets */
#define V2M_SYSREGS_BASE UL(0x0C010000)
#define V2M_SYS_LED U(0x8)
/*
* V2M sysled bit definitions. The values written to this
* register are defined in arch.h & runtime_svc.h. Only
* used by the primary cpu to diagnose any cold boot issues.
*
* SYS_LED[0] - Security state (S=0/NS=1)
* SYS_LED[2:1] - Exception Level (EL3-EL0)
* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
*
*/
#define V2M_SYS_LED_SS_SHIFT U(0)
#define V2M_SYS_LED_EL_SHIFT U(1)
#define V2M_SYS_LED_EC_SHIFT U(3)
#define V2M_SYS_LED_SS_MASK U(0x01)
#define V2M_SYS_LED_EL_MASK U(0x03)
#define V2M_SYS_LED_EC_MASK U(0x1f)
/* NOR Flash */
#define V2M_FLASH0_BASE UL(0x08000000)
#define V2M_FLASH0_SIZE UL(0x04000000)
#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
/*
* The flash can be mapped either as read-only or read-write.
*
* If it is read-write then it should also be mapped as device memory because
* NOR flash programming involves sending a fixed, ordered sequence of commands.
*
* If it is read-only then it should also be mapped as:
* - Normal memory, because reading from NOR flash is transparent, it is like
* reading from RAM.
* - Non-executable by default. If some parts of the flash need to be executable
* then platform code is responsible for re-mapping the appropriate portion
* of it as executable.
*/
#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_RO_DATA | MT_SECURE)
#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
/* Platform ID address */
#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
/* Platform ID related accessors */
#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#define BOARD_CSS_GET_PLAT_TYPE(addr) \
((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
#endif /* __ASSEMBLER__ */
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
/* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
#endif /* SGI_SOC_CSS_DEF_V2_H */

15
plat/arm/css/sgi/include/sgi_soc_platform_def.h Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_SOC_PLATFORM_DEF_H
#define SGI_SOC_PLATFORM_DEF_H
#include <sgi_base_platform_def.h>
#include <plat/arm/board/common/board_css_def.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
#endif /* SGI_SOC_PLATFORM_DEF_H */

13
plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h Normal file
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@ -0,0 +1,13 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_SOC_PLATFORM_DEF_V2_H
#define SGI_SOC_PLATFORM_DEF_V2_H
#include <sgi_base_platform_def.h>
#include <sgi_soc_css_def_v2.h>
#endif /* SGI_SOC_PLATFORM_DEF_V2_H */

3
plat/arm/css/sgi/include/sgi_variant.h
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@ -17,6 +17,9 @@
/* SID Version values for RD-Daniel */
#define RD_DANIEL_SID_VER_PART_NUM 0x078a
/* SID Version values for RD-N2 */
#define RD_N2_SID_VER_PART_NUM 0x07B7
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {
unsigned int platform_id; /* Part Number of the platform */

3
plat/arm/css/sgi/sgi-common.mk
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@ -32,8 +32,7 @@ ENT_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \
${CSS_ENT_BASE}/aarch64/sgi_helper.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/aarch64/sgi_helper.S
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
drivers/arm/sbsa/sbsa.c

3
plat/arm/css/sgi/sgi_bl31_setup.c
View File

@ -74,7 +74,8 @@ static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info[] = {
scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) {
sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(rd_n1e1_edge_scmi_plat_info))
panic();
return &rd_n1e1_edge_scmi_plat_info[channel_id];

85
plat/arm/css/sgi/sgi_plat_v2.c Normal file
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@ -0,0 +1,85 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
/*
* Table of regions for different BL stages to map using the MMU.
*/
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
SGI_MAP_FLASH0_RO,
CSS_SGI_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
{0}
};
#endif
#if IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
SGI_MAP_FLASH0_RO,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
CSS_SGI_MAP_DEVICE,
SOC_MEMCNTRL_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
{0}
};
#endif
#if IMAGE_BL31
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
CSS_SGI_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
{0}
};
#endif
ARM_CASSERT_MMAP
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
assert(heap_size != NULL);
return arm_get_mbedtls_heap(heap_addr, heap_size);
}
#endif
void plat_arm_secure_wdt_start(void)
{
sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
}
void plat_arm_secure_wdt_stop(void)
{
sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
}