zynqmp: pm: Reimplement clock get state (status) EEMI API
Clock get state EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux is_enabled method for PLLs still uses clock get state API get the PLL state, in the implementation of pm_clock_getstate() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock whose state of the gate should be returned. For case 1) we'll call pm_api_clock_pll_getstate() implemented in pm_api_clock.h/c. This function will query the PLL state from PMU using the system-level PLL get mode EEMI API. For case 2) we'll call the PMU to query the clock gate state using system-level clock get status EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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@ -2665,94 +2665,35 @@ enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
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}
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/**
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/**
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* pm_api_get_pll_state() - Get state of PLL
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* pm_clock_pll_get_state - Get state of the PLL
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* @clock_id Id of the PLL
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* @pll Pointer to the target PLL structure
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* @state State of PLL(1: Enable, 0: Reset)
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* @state Location to store the state: 1/0 ("Enabled"/"Disabled")
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*
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*
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* This function is to check state of PLL.
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* "Enable" actually means that the PLL is locked and its bypass is deasserted,
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* "Disable" means that it is bypassed.
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*
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* Return: PM_RET_ERROR_ARGS error if the argument is not valid, success if
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* returned state value is valid or an error if returned by PMU
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*/
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*/
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static inline enum pm_ret_status pm_api_get_pll_state(unsigned int clock_id,
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enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
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unsigned int *state)
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unsigned int *state)
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{
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{
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enum pm_ret_status ret = PM_RET_SUCCESS;
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enum pm_ret_status status;
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unsigned int reg, val;
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enum pm_pll_mode mode;
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reg = clocks[clock_id].control_reg;
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if (!pll || !state)
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ret = pm_mmio_read(reg, &val);
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/* state:
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* 1 - PLL is enabled
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* 0 - PLL is in reset state
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*/
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*state = !(val & PLLCTRL_RESET_MASK);
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return ret;
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}
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/**
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* pm_api_get_clk_state() - Get the state of clock for given id
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* @clock_id: Id of the clock to be enabled
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* @state: Enable(1)/Disable(0)
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*
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* This function is to get state of the clock which is not PLL.
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*
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* Return: Returns status, either success or error+reason.
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*/
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static enum pm_ret_status pm_api_get_clk_state(unsigned int clock_id,
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unsigned int *state)
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{
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enum pm_ret_status ret = PM_RET_SUCCESS;
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struct pm_clock_node *nodes = *clocks[clock_id].nodes;
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uint8_t num_nodes = clocks[clock_id].num_nodes;
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unsigned int reg, val;
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uint8_t i = 0;
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uint8_t offset = NA_SHIFT, width = NA_WIDTH;
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reg = clocks[clock_id].control_reg;
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for (i = 0; i < num_nodes; i++) {
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if (nodes->type == TYPE_GATE) {
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offset = nodes->offset;
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width = nodes->width;
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}
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nodes++;
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}
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if (width == NA_WIDTH)
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return PM_RET_ERROR_NOTSUPPORTED;
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ret = pm_mmio_read(reg, &val);
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*state = (val & BIT_MASK(offset, width)) >> offset;
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return ret;
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}
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/**
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* pm_api_clock_getstate - Get the clock state for given id
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* @clock_id Id of the clock to be queried
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* @state 1/0 (Enabled/Disabled)
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*
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* This function is used by master to get the state of clock
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* including peripherals and PLL clocks.
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*
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* Return: Returns status, either success or error+reason.
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*/
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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unsigned int *state)
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{
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enum pm_ret_status ret = PM_RET_SUCCESS;
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if (!pm_clock_valid(clock_id))
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return PM_RET_ERROR_ARGS;
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return PM_RET_ERROR_ARGS;
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if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
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status = pm_pll_get_mode(pll->nid, &mode);
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return PM_RET_ERROR_NOTSUPPORTED;
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if (status != PM_RET_SUCCESS)
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return status;
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if (ISPLL(clock_id))
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if (mode == PM_PLL_MODE_RESET)
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ret = pm_api_get_pll_state(clock_id, state);
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*state = 0;
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else
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else
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ret = pm_api_get_clk_state(clock_id, state);
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*state = 1;
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return ret;
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return PM_RET_SUCCESS;
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}
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}
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static enum pm_ret_status pm_api_clk_set_divider(unsigned int clock_id,
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static enum pm_ret_status pm_api_clk_set_divider(unsigned int clock_id,
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@ -297,8 +297,9 @@ enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
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unsigned int *state);
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unsigned int *state);
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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unsigned int divider);
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unsigned int divider);
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enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
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enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
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@ -932,7 +932,23 @@ enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
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enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
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unsigned int *state)
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unsigned int *state)
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{
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{
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return pm_api_clock_getstate(clock_id, state);
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struct pm_pll *pll;
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uint32_t payload[PAYLOAD_ARG_CNT];
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enum pm_ret_status status;
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/* First try to handle it as a PLL */
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pll = pm_clock_get_pll(clock_id);
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if (pll)
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return pm_clock_pll_get_state(pll, state);
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/* Check if clock ID is a valid on-chip clock */
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status = pm_clock_id_is_valid(clock_id);
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if (status != PM_RET_SUCCESS)
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return status;
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/* Send request to the PMU */
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PM_PACK_PAYLOAD2(payload, PM_CLOCK_GETSTATE, clock_id);
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return pm_ipi_send_sync(primary_proc, payload, state, 1);
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}
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}
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/**
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/**
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