zynqmp: pm: Add APIs for pin control queries
Add pin control APIs which driver can use to query pin information from firmware. Using these APIs, driver do not need to maintain hard-coded pin database. Major changes in patch are: - Add pin database with pins, functions and function groups information - Implement APIs for pin information queries - Update pin control APIs for get/set functions to use new pin control database. Remove pin database which was added earlier. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
This commit is contained in:
Rajan Vaja
Jolly Shah
parent
63eb7a367d
commit
bd99265b06
File diff suppressed because it is too large
Load Diff
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@ -13,6 +13,662 @@
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#include "pm_common.h"
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#define FUNCTION_NAME_LEN 16
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#define GROUPS_PAYLOAD_LEN 12
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#define NUM_GROUPS_PER_RESP 6
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#define END_OF_FUNCTION "END_OF_FUNCTION"
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#define END_OF_GROUPS -1
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#define PINCTRL_GRP_RESERVED -2
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enum pinctrl_fids {
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PINCTRL_FUNC_CAN0,
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PINCTRL_FUNC_CAN1,
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PINCTRL_FUNC_ETHERNET0,
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PINCTRL_FUNC_ETHERNET1,
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PINCTRL_FUNC_ETHERNET2,
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PINCTRL_FUNC_ETHERNET3,
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PINCTRL_FUNC_GEMTSU0,
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PINCTRL_FUNC_GPIO0,
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PINCTRL_FUNC_I2C0,
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PINCTRL_FUNC_I2C1,
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PINCTRL_FUNC_MDIO0,
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PINCTRL_FUNC_MDIO1,
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PINCTRL_FUNC_MDIO2,
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PINCTRL_FUNC_MDIO3,
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PINCTRL_FUNC_QSPI0,
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PINCTRL_FUNC_QSPI_FBCLK,
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PINCTRL_FUNC_QSPI_SS,
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PINCTRL_FUNC_SPI0,
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PINCTRL_FUNC_SPI1,
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PINCTRL_FUNC_SPI0_SS,
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PINCTRL_FUNC_SPI1_SS,
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PINCTRL_FUNC_SDIO0,
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PINCTRL_FUNC_SDIO0_PC,
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PINCTRL_FUNC_SDIO0_CD,
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PINCTRL_FUNC_SDIO0_WP,
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PINCTRL_FUNC_SDIO1,
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PINCTRL_FUNC_SDIO1_PC,
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PINCTRL_FUNC_SDIO1_CD,
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PINCTRL_FUNC_SDIO1_WP,
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PINCTRL_FUNC_NAND0,
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PINCTRL_FUNC_NAND0_CE,
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PINCTRL_FUNC_NAND0_RB,
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PINCTRL_FUNC_NAND0_DQS,
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PINCTRL_FUNC_TTC0_CLK,
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PINCTRL_FUNC_TTC0_WAV,
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PINCTRL_FUNC_TTC1_CLK,
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PINCTRL_FUNC_TTC1_WAV,
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PINCTRL_FUNC_TTC2_CLK,
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PINCTRL_FUNC_TTC2_WAV,
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PINCTRL_FUNC_TTC3_CLK,
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PINCTRL_FUNC_TTC3_WAV,
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PINCTRL_FUNC_UART0,
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PINCTRL_FUNC_UART1,
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PINCTRL_FUNC_USB0,
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PINCTRL_FUNC_USB1,
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PINCTRL_FUNC_SWDT0_CLK,
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PINCTRL_FUNC_SWDT0_RST,
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PINCTRL_FUNC_SWDT1_CLK,
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PINCTRL_FUNC_SWDT1_RST,
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PINCTRL_FUNC_PMU0,
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PINCTRL_FUNC_PCIE0,
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PINCTRL_FUNC_CSU0,
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PINCTRL_FUNC_DPAUX0,
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PINCTRL_FUNC_PJTAG0,
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PINCTRL_FUNC_TRACE0,
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PINCTRL_FUNC_TRACE0_CLK,
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PINCTRL_FUNC_TESTSCAN0,
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MAX_FUNCTION,
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};
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enum pinctrl_pin {
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PINCTRL_PIN_0,
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PINCTRL_PIN_1,
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PINCTRL_PIN_2,
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PINCTRL_PIN_3,
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PINCTRL_PIN_4,
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PINCTRL_PIN_5,
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PINCTRL_PIN_6,
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PINCTRL_PIN_7,
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PINCTRL_PIN_8,
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PINCTRL_PIN_9,
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PINCTRL_PIN_10,
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PINCTRL_PIN_11,
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PINCTRL_PIN_12,
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PINCTRL_PIN_13,
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PINCTRL_PIN_14,
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PINCTRL_PIN_15,
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PINCTRL_PIN_16,
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PINCTRL_PIN_17,
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PINCTRL_PIN_18,
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PINCTRL_PIN_19,
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PINCTRL_PIN_20,
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PINCTRL_PIN_21,
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PINCTRL_PIN_22,
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PINCTRL_PIN_23,
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PINCTRL_PIN_24,
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PINCTRL_PIN_25,
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PINCTRL_PIN_26,
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PINCTRL_PIN_27,
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PINCTRL_PIN_28,
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PINCTRL_PIN_29,
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PINCTRL_PIN_30,
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PINCTRL_PIN_31,
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PINCTRL_PIN_32,
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PINCTRL_PIN_33,
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PINCTRL_PIN_34,
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PINCTRL_PIN_35,
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PINCTRL_PIN_36,
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PINCTRL_PIN_37,
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PINCTRL_PIN_38,
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PINCTRL_PIN_39,
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PINCTRL_PIN_40,
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PINCTRL_PIN_41,
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PINCTRL_PIN_42,
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PINCTRL_PIN_43,
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PINCTRL_PIN_44,
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PINCTRL_PIN_45,
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PINCTRL_PIN_46,
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PINCTRL_PIN_47,
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PINCTRL_PIN_48,
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PINCTRL_PIN_49,
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PINCTRL_PIN_50,
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PINCTRL_PIN_51,
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PINCTRL_PIN_52,
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PINCTRL_PIN_53,
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PINCTRL_PIN_54,
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PINCTRL_PIN_55,
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PINCTRL_PIN_56,
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PINCTRL_PIN_57,
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PINCTRL_PIN_58,
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PINCTRL_PIN_59,
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PINCTRL_PIN_60,
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PINCTRL_PIN_61,
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PINCTRL_PIN_62,
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PINCTRL_PIN_63,
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PINCTRL_PIN_64,
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PINCTRL_PIN_65,
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PINCTRL_PIN_66,
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PINCTRL_PIN_67,
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PINCTRL_PIN_68,
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PINCTRL_PIN_69,
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PINCTRL_PIN_70,
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PINCTRL_PIN_71,
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PINCTRL_PIN_72,
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PINCTRL_PIN_73,
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PINCTRL_PIN_74,
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PINCTRL_PIN_75,
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PINCTRL_PIN_76,
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PINCTRL_PIN_77,
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MAX_PIN,
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};
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enum pinctrl_group_ids {
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PINCTRL_GRP_ETHERNET0_0,
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PINCTRL_GRP_ETHERNET1_0,
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PINCTRL_GRP_ETHERNET2_0,
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PINCTRL_GRP_ETHERNET3_0,
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PINCTRL_GRP_GEMTSU0_0,
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PINCTRL_GRP_GEMTSU0_1,
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PINCTRL_GRP_GEMTSU0_2,
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PINCTRL_GRP_MDIO0_0,
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PINCTRL_GRP_MDIO1_0,
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PINCTRL_GRP_MDIO1_1,
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PINCTRL_GRP_MDIO2_0,
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PINCTRL_GRP_MDIO3_0,
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PINCTRL_GRP_QSPI0_0,
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PINCTRL_GRP_QSPI_SS,
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PINCTRL_GRP_QSPI_FBCLK,
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PINCTRL_GRP_SPI0_0,
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PINCTRL_GRP_SPI0_0_SS0,
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PINCTRL_GRP_SPI0_0_SS1,
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PINCTRL_GRP_SPI0_0_SS2,
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PINCTRL_GRP_SPI0_1,
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PINCTRL_GRP_SPI0_1_SS0,
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PINCTRL_GRP_SPI0_1_SS1,
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PINCTRL_GRP_SPI0_1_SS2,
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PINCTRL_GRP_SPI0_2,
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PINCTRL_GRP_SPI0_2_SS0,
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PINCTRL_GRP_SPI0_2_SS1,
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PINCTRL_GRP_SPI0_2_SS2,
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PINCTRL_GRP_SPI0_3,
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PINCTRL_GRP_SPI0_3_SS0,
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PINCTRL_GRP_SPI0_3_SS1,
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PINCTRL_GRP_SPI0_3_SS2,
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PINCTRL_GRP_SPI0_4,
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PINCTRL_GRP_SPI0_4_SS0,
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PINCTRL_GRP_SPI0_4_SS1,
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PINCTRL_GRP_SPI0_4_SS2,
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PINCTRL_GRP_SPI0_5,
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PINCTRL_GRP_SPI0_5_SS0,
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PINCTRL_GRP_SPI0_5_SS1,
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PINCTRL_GRP_SPI0_5_SS2,
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PINCTRL_GRP_SPI1_0,
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PINCTRL_GRP_SPI1_0_SS0,
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PINCTRL_GRP_SPI1_0_SS1,
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PINCTRL_GRP_SPI1_0_SS2,
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PINCTRL_GRP_SPI1_1,
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PINCTRL_GRP_SPI1_1_SS0,
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PINCTRL_GRP_SPI1_1_SS1,
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PINCTRL_GRP_SPI1_1_SS2,
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PINCTRL_GRP_SPI1_2,
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PINCTRL_GRP_SPI1_2_SS0,
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PINCTRL_GRP_SPI1_2_SS1,
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PINCTRL_GRP_SPI1_2_SS2,
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PINCTRL_GRP_SPI1_3,
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PINCTRL_GRP_SPI1_3_SS0,
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PINCTRL_GRP_SPI1_3_SS1,
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PINCTRL_GRP_SPI1_3_SS2,
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PINCTRL_GRP_SPI1_4,
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PINCTRL_GRP_SPI1_4_SS0,
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PINCTRL_GRP_SPI1_4_SS1,
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PINCTRL_GRP_SPI1_4_SS2,
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PINCTRL_GRP_SPI1_5,
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PINCTRL_GRP_SPI1_5_SS0,
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PINCTRL_GRP_SPI1_5_SS1,
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PINCTRL_GRP_SPI1_5_SS2,
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PINCTRL_GRP_SDIO0_0,
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PINCTRL_GRP_SDIO0_4BIT_0_0,
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PINCTRL_GRP_SDIO0_4BIT_0_1,
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PINCTRL_GRP_SDIO0_1BIT_0_0,
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PINCTRL_GRP_SDIO0_1BIT_0_1,
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PINCTRL_GRP_SDIO0_1BIT_0_2,
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PINCTRL_GRP_SDIO0_1BIT_0_3,
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PINCTRL_GRP_SDIO0_1BIT_0_4,
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PINCTRL_GRP_SDIO0_1BIT_0_5,
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PINCTRL_GRP_SDIO0_1BIT_0_6,
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PINCTRL_GRP_SDIO0_1BIT_0_7,
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PINCTRL_GRP_SDIO0_0_PC,
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PINCTRL_GRP_SDIO0_0_CD,
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PINCTRL_GRP_SDIO0_0_WP,
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PINCTRL_GRP_SDIO0_1,
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PINCTRL_GRP_SDIO0_4BIT_1_0,
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PINCTRL_GRP_SDIO0_4BIT_1_1,
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PINCTRL_GRP_SDIO0_1BIT_1_0,
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PINCTRL_GRP_SDIO0_1BIT_1_1,
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PINCTRL_GRP_SDIO0_1BIT_1_2,
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PINCTRL_GRP_SDIO0_1BIT_1_3,
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PINCTRL_GRP_SDIO0_1BIT_1_4,
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PINCTRL_GRP_SDIO0_1BIT_1_5,
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PINCTRL_GRP_SDIO0_1BIT_1_6,
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PINCTRL_GRP_SDIO0_1BIT_1_7,
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PINCTRL_GRP_SDIO0_1_PC,
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PINCTRL_GRP_SDIO0_1_CD,
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PINCTRL_GRP_SDIO0_1_WP,
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PINCTRL_GRP_SDIO0_2,
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PINCTRL_GRP_SDIO0_4BIT_2_0,
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PINCTRL_GRP_SDIO0_4BIT_2_1,
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PINCTRL_GRP_SDIO0_1BIT_2_0,
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PINCTRL_GRP_SDIO0_1BIT_2_1,
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PINCTRL_GRP_SDIO0_1BIT_2_2,
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PINCTRL_GRP_SDIO0_1BIT_2_3,
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PINCTRL_GRP_SDIO0_1BIT_2_4,
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PINCTRL_GRP_SDIO0_1BIT_2_5,
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PINCTRL_GRP_SDIO0_1BIT_2_6,
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PINCTRL_GRP_SDIO0_1BIT_2_7,
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PINCTRL_GRP_SDIO0_2_PC,
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PINCTRL_GRP_SDIO0_2_CD,
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PINCTRL_GRP_SDIO0_2_WP,
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PINCTRL_GRP_SDIO1_0,
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PINCTRL_GRP_SDIO1_4BIT_0_0,
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PINCTRL_GRP_SDIO1_4BIT_0_1,
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PINCTRL_GRP_SDIO1_1BIT_0_0,
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PINCTRL_GRP_SDIO1_1BIT_0_1,
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PINCTRL_GRP_SDIO1_1BIT_0_2,
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PINCTRL_GRP_SDIO1_1BIT_0_3,
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PINCTRL_GRP_SDIO1_1BIT_0_4,
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PINCTRL_GRP_SDIO1_1BIT_0_5,
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PINCTRL_GRP_SDIO1_1BIT_0_6,
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PINCTRL_GRP_SDIO1_1BIT_0_7,
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PINCTRL_GRP_SDIO1_0_PC,
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PINCTRL_GRP_SDIO1_0_CD,
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PINCTRL_GRP_SDIO1_0_WP,
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PINCTRL_GRP_SDIO1_4BIT_1_0,
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PINCTRL_GRP_SDIO1_1BIT_1_0,
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PINCTRL_GRP_SDIO1_1BIT_1_1,
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PINCTRL_GRP_SDIO1_1BIT_1_2,
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PINCTRL_GRP_SDIO1_1BIT_1_3,
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PINCTRL_GRP_SDIO1_1_PC,
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PINCTRL_GRP_SDIO1_1_CD,
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PINCTRL_GRP_SDIO1_1_WP,
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PINCTRL_GRP_NAND0_0,
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PINCTRL_GRP_NAND0_0_CE,
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PINCTRL_GRP_NAND0_0_RB,
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PINCTRL_GRP_NAND0_0_DQS,
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PINCTRL_GRP_NAND0_1_CE,
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PINCTRL_GRP_NAND0_1_RB,
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PINCTRL_GRP_NAND0_1_DQS,
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PINCTRL_GRP_CAN0_0,
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PINCTRL_GRP_CAN0_1,
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PINCTRL_GRP_CAN0_2,
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PINCTRL_GRP_CAN0_3,
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PINCTRL_GRP_CAN0_4,
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PINCTRL_GRP_CAN0_5,
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PINCTRL_GRP_CAN0_6,
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PINCTRL_GRP_CAN0_7,
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PINCTRL_GRP_CAN0_8,
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PINCTRL_GRP_CAN0_9,
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PINCTRL_GRP_CAN0_10,
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PINCTRL_GRP_CAN0_11,
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PINCTRL_GRP_CAN0_12,
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PINCTRL_GRP_CAN0_13,
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PINCTRL_GRP_CAN0_14,
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PINCTRL_GRP_CAN0_15,
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PINCTRL_GRP_CAN0_16,
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PINCTRL_GRP_CAN0_17,
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PINCTRL_GRP_CAN0_18,
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PINCTRL_GRP_CAN1_0,
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PINCTRL_GRP_CAN1_1,
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PINCTRL_GRP_CAN1_2,
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PINCTRL_GRP_CAN1_3,
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PINCTRL_GRP_CAN1_4,
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PINCTRL_GRP_CAN1_5,
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PINCTRL_GRP_CAN1_6,
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PINCTRL_GRP_CAN1_7,
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PINCTRL_GRP_CAN1_8,
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PINCTRL_GRP_CAN1_9,
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PINCTRL_GRP_CAN1_10,
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PINCTRL_GRP_CAN1_11,
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PINCTRL_GRP_CAN1_12,
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PINCTRL_GRP_CAN1_13,
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PINCTRL_GRP_CAN1_14,
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PINCTRL_GRP_CAN1_15,
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PINCTRL_GRP_CAN1_16,
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PINCTRL_GRP_CAN1_17,
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PINCTRL_GRP_CAN1_18,
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PINCTRL_GRP_CAN1_19,
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PINCTRL_GRP_UART0_0,
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PINCTRL_GRP_UART0_1,
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PINCTRL_GRP_UART0_2,
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PINCTRL_GRP_UART0_3,
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PINCTRL_GRP_UART0_4,
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PINCTRL_GRP_UART0_5,
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PINCTRL_GRP_UART0_6,
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PINCTRL_GRP_UART0_7,
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PINCTRL_GRP_UART0_8,
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PINCTRL_GRP_UART0_9,
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PINCTRL_GRP_UART0_10,
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PINCTRL_GRP_UART0_11,
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PINCTRL_GRP_UART0_12,
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PINCTRL_GRP_UART0_13,
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PINCTRL_GRP_UART0_14,
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PINCTRL_GRP_UART0_15,
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PINCTRL_GRP_UART0_16,
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PINCTRL_GRP_UART0_17,
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PINCTRL_GRP_UART0_18,
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PINCTRL_GRP_UART1_0,
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PINCTRL_GRP_UART1_1,
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PINCTRL_GRP_UART1_2,
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PINCTRL_GRP_UART1_3,
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PINCTRL_GRP_UART1_4,
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PINCTRL_GRP_UART1_5,
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PINCTRL_GRP_UART1_6,
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PINCTRL_GRP_UART1_7,
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PINCTRL_GRP_UART1_8,
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PINCTRL_GRP_UART1_9,
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PINCTRL_GRP_UART1_10,
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PINCTRL_GRP_UART1_11,
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PINCTRL_GRP_UART1_12,
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PINCTRL_GRP_UART1_13,
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PINCTRL_GRP_UART1_14,
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PINCTRL_GRP_UART1_15,
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PINCTRL_GRP_UART1_16,
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PINCTRL_GRP_UART1_17,
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PINCTRL_GRP_UART1_18,
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PINCTRL_GRP_I2C0_0,
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PINCTRL_GRP_I2C0_1,
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PINCTRL_GRP_I2C0_2,
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PINCTRL_GRP_I2C0_3,
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PINCTRL_GRP_I2C0_4,
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PINCTRL_GRP_I2C0_5,
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PINCTRL_GRP_I2C0_6,
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PINCTRL_GRP_I2C0_7,
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PINCTRL_GRP_I2C0_8,
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PINCTRL_GRP_I2C0_9,
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PINCTRL_GRP_I2C0_10,
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PINCTRL_GRP_I2C0_11,
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PINCTRL_GRP_I2C0_12,
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PINCTRL_GRP_I2C0_13,
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PINCTRL_GRP_I2C0_14,
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PINCTRL_GRP_I2C0_15,
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PINCTRL_GRP_I2C0_16,
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PINCTRL_GRP_I2C0_17,
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PINCTRL_GRP_I2C0_18,
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PINCTRL_GRP_I2C1_0,
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PINCTRL_GRP_I2C1_1,
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PINCTRL_GRP_I2C1_2,
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PINCTRL_GRP_I2C1_3,
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PINCTRL_GRP_I2C1_4,
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PINCTRL_GRP_I2C1_5,
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PINCTRL_GRP_I2C1_6,
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PINCTRL_GRP_I2C1_7,
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PINCTRL_GRP_I2C1_8,
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PINCTRL_GRP_I2C1_9,
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PINCTRL_GRP_I2C1_10,
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PINCTRL_GRP_I2C1_11,
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PINCTRL_GRP_I2C1_12,
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PINCTRL_GRP_I2C1_13,
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PINCTRL_GRP_I2C1_14,
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PINCTRL_GRP_I2C1_15,
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PINCTRL_GRP_I2C1_16,
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PINCTRL_GRP_I2C1_17,
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PINCTRL_GRP_I2C1_18,
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PINCTRL_GRP_I2C1_19,
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PINCTRL_GRP_TTC0_0_CLK,
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PINCTRL_GRP_TTC0_0_WAV,
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PINCTRL_GRP_TTC0_1_CLK,
|
||||
PINCTRL_GRP_TTC0_1_WAV,
|
||||
PINCTRL_GRP_TTC0_2_CLK,
|
||||
PINCTRL_GRP_TTC0_2_WAV,
|
||||
PINCTRL_GRP_TTC0_3_CLK,
|
||||
PINCTRL_GRP_TTC0_3_WAV,
|
||||
PINCTRL_GRP_TTC0_4_CLK,
|
||||
PINCTRL_GRP_TTC0_4_WAV,
|
||||
PINCTRL_GRP_TTC0_5_CLK,
|
||||
PINCTRL_GRP_TTC0_5_WAV,
|
||||
PINCTRL_GRP_TTC0_6_CLK,
|
||||
PINCTRL_GRP_TTC0_6_WAV,
|
||||
PINCTRL_GRP_TTC0_7_CLK,
|
||||
PINCTRL_GRP_TTC0_7_WAV,
|
||||
PINCTRL_GRP_TTC0_8_CLK,
|
||||
PINCTRL_GRP_TTC0_8_WAV,
|
||||
PINCTRL_GRP_TTC1_0_CLK,
|
||||
PINCTRL_GRP_TTC1_0_WAV,
|
||||
PINCTRL_GRP_TTC1_1_CLK,
|
||||
PINCTRL_GRP_TTC1_1_WAV,
|
||||
PINCTRL_GRP_TTC1_2_CLK,
|
||||
PINCTRL_GRP_TTC1_2_WAV,
|
||||
PINCTRL_GRP_TTC1_3_CLK,
|
||||
PINCTRL_GRP_TTC1_3_WAV,
|
||||
PINCTRL_GRP_TTC1_4_CLK,
|
||||
PINCTRL_GRP_TTC1_4_WAV,
|
||||
PINCTRL_GRP_TTC1_5_CLK,
|
||||
PINCTRL_GRP_TTC1_5_WAV,
|
||||
PINCTRL_GRP_TTC1_6_CLK,
|
||||
PINCTRL_GRP_TTC1_6_WAV,
|
||||
PINCTRL_GRP_TTC1_7_CLK,
|
||||
PINCTRL_GRP_TTC1_7_WAV,
|
||||
PINCTRL_GRP_TTC1_8_CLK,
|
||||
PINCTRL_GRP_TTC1_8_WAV,
|
||||
PINCTRL_GRP_TTC2_0_CLK,
|
||||
PINCTRL_GRP_TTC2_0_WAV,
|
||||
PINCTRL_GRP_TTC2_1_CLK,
|
||||
PINCTRL_GRP_TTC2_1_WAV,
|
||||
PINCTRL_GRP_TTC2_2_CLK,
|
||||
PINCTRL_GRP_TTC2_2_WAV,
|
||||
PINCTRL_GRP_TTC2_3_CLK,
|
||||
PINCTRL_GRP_TTC2_3_WAV,
|
||||
PINCTRL_GRP_TTC2_4_CLK,
|
||||
PINCTRL_GRP_TTC2_4_WAV,
|
||||
PINCTRL_GRP_TTC2_5_CLK,
|
||||
PINCTRL_GRP_TTC2_5_WAV,
|
||||
PINCTRL_GRP_TTC2_6_CLK,
|
||||
PINCTRL_GRP_TTC2_6_WAV,
|
||||
PINCTRL_GRP_TTC2_7_CLK,
|
||||
PINCTRL_GRP_TTC2_7_WAV,
|
||||
PINCTRL_GRP_TTC2_8_CLK,
|
||||
PINCTRL_GRP_TTC2_8_WAV,
|
||||
PINCTRL_GRP_TTC3_0_CLK,
|
||||
PINCTRL_GRP_TTC3_0_WAV,
|
||||
PINCTRL_GRP_TTC3_1_CLK,
|
||||
PINCTRL_GRP_TTC3_1_WAV,
|
||||
PINCTRL_GRP_TTC3_2_CLK,
|
||||
PINCTRL_GRP_TTC3_2_WAV,
|
||||
PINCTRL_GRP_TTC3_3_CLK,
|
||||
PINCTRL_GRP_TTC3_3_WAV,
|
||||
PINCTRL_GRP_TTC3_4_CLK,
|
||||
PINCTRL_GRP_TTC3_4_WAV,
|
||||
PINCTRL_GRP_TTC3_5_CLK,
|
||||
PINCTRL_GRP_TTC3_5_WAV,
|
||||
PINCTRL_GRP_TTC3_6_CLK,
|
||||
PINCTRL_GRP_TTC3_6_WAV,
|
||||
PINCTRL_GRP_TTC3_7_CLK,
|
||||
PINCTRL_GRP_TTC3_7_WAV,
|
||||
PINCTRL_GRP_TTC3_8_CLK,
|
||||
PINCTRL_GRP_TTC3_8_WAV,
|
||||
PINCTRL_GRP_SWDT0_0_CLK,
|
||||
PINCTRL_GRP_SWDT0_0_RST,
|
||||
PINCTRL_GRP_SWDT0_1_CLK,
|
||||
PINCTRL_GRP_SWDT0_1_RST,
|
||||
PINCTRL_GRP_SWDT0_2_CLK,
|
||||
PINCTRL_GRP_SWDT0_2_RST,
|
||||
PINCTRL_GRP_SWDT0_3_CLK,
|
||||
PINCTRL_GRP_SWDT0_3_RST,
|
||||
PINCTRL_GRP_SWDT0_4_CLK,
|
||||
PINCTRL_GRP_SWDT0_4_RST,
|
||||
PINCTRL_GRP_SWDT0_5_CLK,
|
||||
PINCTRL_GRP_SWDT0_5_RST,
|
||||
PINCTRL_GRP_SWDT0_6_CLK,
|
||||
PINCTRL_GRP_SWDT0_6_RST,
|
||||
PINCTRL_GRP_SWDT0_7_CLK,
|
||||
PINCTRL_GRP_SWDT0_7_RST,
|
||||
PINCTRL_GRP_SWDT0_8_CLK,
|
||||
PINCTRL_GRP_SWDT0_8_RST,
|
||||
PINCTRL_GRP_SWDT0_9_CLK,
|
||||
PINCTRL_GRP_SWDT0_9_RST,
|
||||
PINCTRL_GRP_SWDT0_10_CLK,
|
||||
PINCTRL_GRP_SWDT0_10_RST,
|
||||
PINCTRL_GRP_SWDT0_11_CLK,
|
||||
PINCTRL_GRP_SWDT0_11_RST,
|
||||
PINCTRL_GRP_SWDT0_12_CLK,
|
||||
PINCTRL_GRP_SWDT0_12_RST,
|
||||
PINCTRL_GRP_SWDT1_0_CLK,
|
||||
PINCTRL_GRP_SWDT1_0_RST,
|
||||
PINCTRL_GRP_SWDT1_1_CLK,
|
||||
PINCTRL_GRP_SWDT1_1_RST,
|
||||
PINCTRL_GRP_SWDT1_2_CLK,
|
||||
PINCTRL_GRP_SWDT1_2_RST,
|
||||
PINCTRL_GRP_SWDT1_3_CLK,
|
||||
PINCTRL_GRP_SWDT1_3_RST,
|
||||
PINCTRL_GRP_SWDT1_4_CLK,
|
||||
PINCTRL_GRP_SWDT1_4_RST,
|
||||
PINCTRL_GRP_SWDT1_5_CLK,
|
||||
PINCTRL_GRP_SWDT1_5_RST,
|
||||
PINCTRL_GRP_SWDT1_6_CLK,
|
||||
PINCTRL_GRP_SWDT1_6_RST,
|
||||
PINCTRL_GRP_SWDT1_7_CLK,
|
||||
PINCTRL_GRP_SWDT1_7_RST,
|
||||
PINCTRL_GRP_SWDT1_8_CLK,
|
||||
PINCTRL_GRP_SWDT1_8_RST,
|
||||
PINCTRL_GRP_SWDT1_9_CLK,
|
||||
PINCTRL_GRP_SWDT1_9_RST,
|
||||
PINCTRL_GRP_SWDT1_10_CLK,
|
||||
PINCTRL_GRP_SWDT1_10_RST,
|
||||
PINCTRL_GRP_SWDT1_11_CLK,
|
||||
PINCTRL_GRP_SWDT1_11_RST,
|
||||
PINCTRL_GRP_SWDT1_12_CLK,
|
||||
PINCTRL_GRP_SWDT1_12_RST,
|
||||
PINCTRL_GRP_GPIO0_0,
|
||||
PINCTRL_GRP_GPIO0_1,
|
||||
PINCTRL_GRP_GPIO0_2,
|
||||
PINCTRL_GRP_GPIO0_3,
|
||||
PINCTRL_GRP_GPIO0_4,
|
||||
PINCTRL_GRP_GPIO0_5,
|
||||
PINCTRL_GRP_GPIO0_6,
|
||||
PINCTRL_GRP_GPIO0_7,
|
||||
PINCTRL_GRP_GPIO0_8,
|
||||
PINCTRL_GRP_GPIO0_9,
|
||||
PINCTRL_GRP_GPIO0_10,
|
||||
PINCTRL_GRP_GPIO0_11,
|
||||
PINCTRL_GRP_GPIO0_12,
|
||||
PINCTRL_GRP_GPIO0_13,
|
||||
PINCTRL_GRP_GPIO0_14,
|
||||
PINCTRL_GRP_GPIO0_15,
|
||||
PINCTRL_GRP_GPIO0_16,
|
||||
PINCTRL_GRP_GPIO0_17,
|
||||
PINCTRL_GRP_GPIO0_18,
|
||||
PINCTRL_GRP_GPIO0_19,
|
||||
PINCTRL_GRP_GPIO0_20,
|
||||
PINCTRL_GRP_GPIO0_21,
|
||||
PINCTRL_GRP_GPIO0_22,
|
||||
PINCTRL_GRP_GPIO0_23,
|
||||
PINCTRL_GRP_GPIO0_24,
|
||||
PINCTRL_GRP_GPIO0_25,
|
||||
PINCTRL_GRP_GPIO0_26,
|
||||
PINCTRL_GRP_GPIO0_27,
|
||||
PINCTRL_GRP_GPIO0_28,
|
||||
PINCTRL_GRP_GPIO0_29,
|
||||
PINCTRL_GRP_GPIO0_30,
|
||||
PINCTRL_GRP_GPIO0_31,
|
||||
PINCTRL_GRP_GPIO0_32,
|
||||
PINCTRL_GRP_GPIO0_33,
|
||||
PINCTRL_GRP_GPIO0_34,
|
||||
PINCTRL_GRP_GPIO0_35,
|
||||
PINCTRL_GRP_GPIO0_36,
|
||||
PINCTRL_GRP_GPIO0_37,
|
||||
PINCTRL_GRP_GPIO0_38,
|
||||
PINCTRL_GRP_GPIO0_39,
|
||||
PINCTRL_GRP_GPIO0_40,
|
||||
PINCTRL_GRP_GPIO0_41,
|
||||
PINCTRL_GRP_GPIO0_42,
|
||||
PINCTRL_GRP_GPIO0_43,
|
||||
PINCTRL_GRP_GPIO0_44,
|
||||
PINCTRL_GRP_GPIO0_45,
|
||||
PINCTRL_GRP_GPIO0_46,
|
||||
PINCTRL_GRP_GPIO0_47,
|
||||
PINCTRL_GRP_GPIO0_48,
|
||||
PINCTRL_GRP_GPIO0_49,
|
||||
PINCTRL_GRP_GPIO0_50,
|
||||
PINCTRL_GRP_GPIO0_51,
|
||||
PINCTRL_GRP_GPIO0_52,
|
||||
PINCTRL_GRP_GPIO0_53,
|
||||
PINCTRL_GRP_GPIO0_54,
|
||||
PINCTRL_GRP_GPIO0_55,
|
||||
PINCTRL_GRP_GPIO0_56,
|
||||
PINCTRL_GRP_GPIO0_57,
|
||||
PINCTRL_GRP_GPIO0_58,
|
||||
PINCTRL_GRP_GPIO0_59,
|
||||
PINCTRL_GRP_GPIO0_60,
|
||||
PINCTRL_GRP_GPIO0_61,
|
||||
PINCTRL_GRP_GPIO0_62,
|
||||
PINCTRL_GRP_GPIO0_63,
|
||||
PINCTRL_GRP_GPIO0_64,
|
||||
PINCTRL_GRP_GPIO0_65,
|
||||
PINCTRL_GRP_GPIO0_66,
|
||||
PINCTRL_GRP_GPIO0_67,
|
||||
PINCTRL_GRP_GPIO0_68,
|
||||
PINCTRL_GRP_GPIO0_69,
|
||||
PINCTRL_GRP_GPIO0_70,
|
||||
PINCTRL_GRP_GPIO0_71,
|
||||
PINCTRL_GRP_GPIO0_72,
|
||||
PINCTRL_GRP_GPIO0_73,
|
||||
PINCTRL_GRP_GPIO0_74,
|
||||
PINCTRL_GRP_GPIO0_75,
|
||||
PINCTRL_GRP_GPIO0_76,
|
||||
PINCTRL_GRP_GPIO0_77,
|
||||
PINCTRL_GRP_USB0_0,
|
||||
PINCTRL_GRP_USB1_0,
|
||||
PINCTRL_GRP_PMU0_0,
|
||||
PINCTRL_GRP_PMU0_1,
|
||||
PINCTRL_GRP_PMU0_2,
|
||||
PINCTRL_GRP_PMU0_3,
|
||||
PINCTRL_GRP_PMU0_4,
|
||||
PINCTRL_GRP_PMU0_5,
|
||||
PINCTRL_GRP_PMU0_6,
|
||||
PINCTRL_GRP_PMU0_7,
|
||||
PINCTRL_GRP_PMU0_8,
|
||||
PINCTRL_GRP_PMU0_9,
|
||||
PINCTRL_GRP_PMU0_10,
|
||||
PINCTRL_GRP_PMU0_11,
|
||||
PINCTRL_GRP_PCIE0_0,
|
||||
PINCTRL_GRP_PCIE0_1,
|
||||
PINCTRL_GRP_PCIE0_2,
|
||||
PINCTRL_GRP_PCIE0_3,
|
||||
PINCTRL_GRP_PCIE0_4,
|
||||
PINCTRL_GRP_PCIE0_5,
|
||||
PINCTRL_GRP_PCIE0_6,
|
||||
PINCTRL_GRP_PCIE0_7,
|
||||
PINCTRL_GRP_CSU0_0,
|
||||
PINCTRL_GRP_CSU0_1,
|
||||
PINCTRL_GRP_CSU0_2,
|
||||
PINCTRL_GRP_CSU0_3,
|
||||
PINCTRL_GRP_CSU0_4,
|
||||
PINCTRL_GRP_CSU0_5,
|
||||
PINCTRL_GRP_CSU0_6,
|
||||
PINCTRL_GRP_CSU0_7,
|
||||
PINCTRL_GRP_CSU0_8,
|
||||
PINCTRL_GRP_CSU0_9,
|
||||
PINCTRL_GRP_CSU0_10,
|
||||
PINCTRL_GRP_CSU0_11,
|
||||
PINCTRL_GRP_DPAUX0_0,
|
||||
PINCTRL_GRP_DPAUX0_1,
|
||||
PINCTRL_GRP_DPAUX0_2,
|
||||
PINCTRL_GRP_DPAUX0_3,
|
||||
PINCTRL_GRP_PJTAG0_0,
|
||||
PINCTRL_GRP_PJTAG0_1,
|
||||
PINCTRL_GRP_PJTAG0_2,
|
||||
PINCTRL_GRP_PJTAG0_3,
|
||||
PINCTRL_GRP_PJTAG0_4,
|
||||
PINCTRL_GRP_PJTAG0_5,
|
||||
PINCTRL_GRP_TRACE0_0,
|
||||
PINCTRL_GRP_TRACE0_0_CLK,
|
||||
PINCTRL_GRP_TRACE0_1,
|
||||
PINCTRL_GRP_TRACE0_1_CLK,
|
||||
PINCTRL_GRP_TRACE0_2,
|
||||
PINCTRL_GRP_TRACE0_2_CLK,
|
||||
PINCTRL_GRP_TESTSCAN0_0,
|
||||
};
|
||||
|
||||
enum pm_pinctrl_config_param {
|
||||
PINCTRL_CONFIG_SLEW_RATE,
|
||||
PINCTRL_CONFIG_BIAS_STATUS,
|
||||
|
|
@ -51,14 +707,25 @@ enum pm_pinctrl_drive_strength {
|
|||
};
|
||||
|
||||
enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
|
||||
enum pm_node_id nid);
|
||||
unsigned int id);
|
||||
enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
|
||||
enum pm_node_id *nid);
|
||||
unsigned int *id);
|
||||
enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int value);
|
||||
enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
|
||||
unsigned int param,
|
||||
unsigned int *value);
|
||||
|
||||
enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
|
||||
char *name);
|
||||
enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
|
||||
unsigned int index,
|
||||
uint16_t *groups);
|
||||
enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin,
|
||||
unsigned int index,
|
||||
uint16_t *groups);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs);
|
||||
enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
|
||||
unsigned int *ngroups);
|
||||
#endif /* _PM_API_PINCTRL_H_ */
|
||||
|
|
|
|||
|
|
@ -894,6 +894,113 @@ enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
|
|||
return pm_api_clock_getparent(clock_id, parent_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_pins - PM call to request number of pins
|
||||
* @npins: Number of pins
|
||||
*
|
||||
* This function is used by master to get number of pins
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_pins(uint32_t *npins)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_pins(npins);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_functions - PM call to request number of functions
|
||||
* @nfuncs: Number of functions
|
||||
*
|
||||
* This function is used by master to get number of functions
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_functions(uint32_t *nfuncs)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_functions(nfuncs);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_num_function_groups - PM call to request number of
|
||||
* function groups
|
||||
* @fid: Id of function
|
||||
* @ngroups: Number of function groups
|
||||
*
|
||||
* This function is used by master to get number of function groups specified
|
||||
* by given function Id
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_num_function_groups(unsigned int fid,
|
||||
uint32_t *ngroups)
|
||||
{
|
||||
return pm_api_pinctrl_get_num_func_groups(fid, ngroups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_function_name - PM call to request function name
|
||||
* @fid: Id of function
|
||||
* @name: Name of function
|
||||
*
|
||||
* This function is used by master to get name of function specified
|
||||
* by given function Id
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_function_name(unsigned int fid,
|
||||
char *name)
|
||||
{
|
||||
return pm_api_pinctrl_get_function_name(fid, name);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_function_groups - PM call to request function groups
|
||||
* @fid: Id of function
|
||||
* @index: Index of next function groups
|
||||
* @groups: Function groups
|
||||
*
|
||||
* This function is used by master to get function groups specified
|
||||
* by given function Id. This API will return 6 function groups with
|
||||
* a single response. To get other function groups, master should call
|
||||
* same API in loop with new function groups index till error is returned.
|
||||
*
|
||||
* E.g First call should have index 0 which will return function groups
|
||||
* 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
|
||||
* function groups 6, 7, 8, 9, 10 and 11 and so on.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_function_groups(unsigned int fid,
|
||||
unsigned int index,
|
||||
uint16_t *groups)
|
||||
{
|
||||
return pm_api_pinctrl_get_function_groups(fid, index, groups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_pinctrl_get_pin_groups - PM call to request pin groups
|
||||
* @pin_id: Id of pin
|
||||
* @index: Index of next pin groups
|
||||
* @groups: pin groups
|
||||
*
|
||||
* This function is used by master to get pin groups specified
|
||||
* by given pin Id. This API will return 6 pin groups with
|
||||
* a single response. To get other pin groups, master should call
|
||||
* same API in loop with new pin groups index till error is returned.
|
||||
*
|
||||
* E.g First call should have index 0 which will return pin groups
|
||||
* 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
|
||||
* pin groups 6, 7, 8, 9, 10 and 11 and so on.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason.
|
||||
*/
|
||||
static enum pm_ret_status pm_pinctrl_get_pin_groups(unsigned int pin_id,
|
||||
unsigned int index,
|
||||
uint16_t *groups)
|
||||
{
|
||||
return pm_api_pinctrl_get_pin_groups(pin_id, index, groups);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_query_data() - PM API for querying firmware data
|
||||
* @arg1 Argument 1 to requested IOCTL call
|
||||
|
|
@ -934,6 +1041,31 @@ enum pm_ret_status pm_query_data(enum pm_query_id qid,
|
|||
ret = pm_clock_get_attributes(arg1, &data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_PINS:
|
||||
ret = pm_pinctrl_get_num_pins(&data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
|
||||
ret = pm_pinctrl_get_num_functions(&data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
|
||||
ret = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_FUNCTION_NAME:
|
||||
ret = pm_pinctrl_get_function_name(arg1, (char *)data);
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
|
||||
ret = pm_pinctrl_get_function_groups(arg1, arg2,
|
||||
(uint16_t *)&data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
case PM_QID_PINCTRL_GET_PIN_GROUPS:
|
||||
ret = pm_pinctrl_get_pin_groups(arg1, arg2,
|
||||
(uint16_t *)&data[1]);
|
||||
data[0] = ret;
|
||||
break;
|
||||
default:
|
||||
ret = PM_RET_ERROR_ARGS;
|
||||
WARN("Unimplemented query service call: 0x%x\n", qid);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,12 @@ enum pm_query_id {
|
|||
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
|
||||
PM_QID_CLOCK_GET_PARENTS,
|
||||
PM_QID_CLOCK_GET_ATTRIBUTES,
|
||||
PM_QID_PINCTRL_GET_NUM_PINS,
|
||||
PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
|
||||
PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
|
||||
PM_QID_PINCTRL_GET_FUNCTION_NAME,
|
||||
PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
|
||||
PM_QID_PINCTRL_GET_PIN_GROUPS,
|
||||
};
|
||||
|
||||
/**********************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue